Resiliency In Action with Self-tuning Processors
posted by Cheryl Miller on September 23, 2009
At Intel Developer Forum, numerous research projects were on display. One of the projects demonstrated a low voltage resilient processor that automatically adapts its power-performance point to achieve the best throughput at minimum energy. One of the recurring themes at this year’s IDF is energy efficiency. It is exciting to see so many projects that are taking proactive steps to be more environmentally conscious.
The attached video demonstrates a low voltage resilient processor that automatically adapts its power-performance point to achieve the best throughput at minimum energy. The distributed sensors and error detectors on the die enable automatic reissue of instructions or automatic adaptation of the operating conditions to achieve error-free performance beyond typical dynamic guardbands set by voltage, temperature and aging over lifetime of the product. This is the first “processor” prototype in Intel’s MG/hi-K 45nm process technology that can run code and has the capability to adapt to changing environment conditions, respond to slow degradations over its lifetime, can detect and correct infrequent failures on the fly in hardware. It promises major gains in energy efficiency and performance under wide dynamic operating conditions depending on its unique usage scenario.
Comments (2)
tagged: IDF09, intel labs, research, self-tuning processor
Comments
Sep 23 | Sundar Srinivasan said:
Sounds awesome. Automatic adaptation for energy efficiency is good on its own. But what is great is that the processor corrects infrequent failures on the fly. How does it do that? Is it some implementation of self-referential Goedel Machine? Please post more on this.
Dec 15 | Timothy Miller said:
It would be nice if they were specific about the nature of their error detector. Some kind of DMR with checkpoint and rollback? RAZOR flipflops? A DIVA-style architecture? What’s interesting about this is that Intel is employing it. Researchers have been studying this problem for a long time, and ARM has been using various error-resiliant techniques for a while too. To someone in the field, this is a combination of “old news” and “finally, Intel got with the program.”