Recently I was looking over some slides by Intel Fellow Vivek De, which he has put together for his Intel Developer Forum session next week on “Energy Management Innovations for Future Multi-Core Processors.” In the presentation I saw a few slides on something called a “Viterbi accelerator.” This is an interesting technology that ties together various aspects our research which I wanted to mention here.
I’d seen this project before: specifically, it was presented last February at ISSCC alongside the 80-core research processor. Looking back at the ISSCC program guide, this technology was presented as: “A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS.” So, at the heart it’s a circuit to perform Viterbi algorithms, which according to all-knowing wikipedia is “an error-correction scheme for noisy digital communication links…used in both CDMA and GSM digital cellular, dial-up modems, satellite, deep-space communications, and 802.11 wireless LANs.” About a month ago I had a chance to talk to the researchers who developed this device at an internal “science fair” that we hold annually at one of our Oregon facilities. What caught my attention was the fact that Sanu and Mark (pictured here ) positioned this Viterbi circuitry as a potential accelerator core for a future tera-scale processor.
Accelerators are a hot topic across Intel and the industry right now, especially since Pat Gelsinger unveiled QuickAssist at Beijing IDF. Here in the labs, we saw some very positive reaction to our Accelerator Exoskeleton project in a series of TG Daily articles (one, two and three).
Publicly we’ve been talking recently about how an on-die interconnect network (such as the one in the 80-core research processor) would enable us to integrate such accelerators much more tightly in the future. This Viterbi accelerator is one example of such accelerator hardware. And because it’s intended primarily to make wireless comms more energy-efficient, this means it is a proof point showing that the tera-scale vision is not just for servers and desktops, but potentially laptops and smaller devices as well.
What makes accelerators interesting is that they can perform a fixed task while consuming much less power than general purpose logic circuits. This particular Viterbi accelerator has an efficiency of 10.8 Gbps/Watt. According to the Mark and Sanu, that’s 10x-100x better than the best reported results using general purpose hardware. This is important, because in a typical chipset today the Viterbi function could consume as much as 40% of the power of the digital comms portion of the chip. Here’s some footage from the lab:
Also, it’s actually not a “fixed” function accelerator. This device is reconfigurable, meaning it can be changed to support the most current protocols. Coupled with similar reconfigurable accelerators for other computation intensive tasks such as encryption methods, speech recognition, search, graphics and computational linguistics, tera-scale performance could be achieved in small devices with much more energy-efficiency than with general-purpose cores alone.
The name “tera-scale” has been very useful to describe our research vision, since it describes the type of capabilities we are driving for in future platforms. To some people it also carries a connotation of “large,” especially since until now tera-scale has been associated primarily with high performance computing (HPC). However the scalability and modularity of tera-scale design methodology is such that the core count and type can be changed to support a variety of future platforms. With the same cores as building blocks, one can imagine building a theoretical server processor with 64 cores, a desktop processor with 32, and a mobile processor with 16 — including some accelerator cores to maximize energy efficiency for the certain often-used tasks in each platform.
