posted by 杜江凌 (John Du) on August 29, 2007
By John Du, reposted from our Chinese language blog.
In my past posts, I’ve talked about Tera-scale computing. Intel has been doing research in both software and hardware on future processor platforms with 10s to 100s of cores. Our objective is to handle the future’s Terabytes applications with powerful enough Tera-scale computing technologies and make the technology more intelligent, more reliable and more useful to humans.
At the same time, instant communication in ever smaller form factors is becoming a critical part of our daily life and work. Intel researchers, including those in our China lab, are doing research in numerous communication technologies with an objective to allow people to communicate more easily and have access to anything they want, when and where they want, and to do so easily, reliably and securely.
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tagged: Broadband, China, ICRC, MIMO, research, wireless
posted by Sean Koehl on August 20, 2007
As an editor of the Research@Intel blog, I sometimes have the opportunity to share a guest post to complement those coming from our regular bloggers. Today’s post comes from Mike Mayberry of Intel’s Technology & Manufacturing Group. Mike is Director of Components Research, the group at Intel which does process technology research.
In this blog, I’ll relate some of the recent advances in compound semiconductors, but first a little background. There’s an old joke that “Gallium Arsenide is the technology of the future, never the technology of the present” and like all jokes there’s a kernel of truth. Unlike silicon, a compound semiconductor is made up of two elements, gallium and arsenic for example (GaAs). Using two elements means more opportunity to tune the materials for performance or optical properties but also makes the challenge of fabricating wafers and processing much more complicated. While 300mm diameter silicon wafers are produced in huge quantities, GaAs wafers are typically 150mm, which translates into a huge cost disadvantage. Consequently today, compound semiconductors are used in smaller scale applications where their special properties outweigh the added costs.
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tagged: Compound semiconductor, Gallium Arsenide, high-k, III-V materials, Moore's Law, silicon, transistor
posted by Anwar Ghuloum (葛安华) on August 17, 2007
In my last blog, I described why parallel programming is hard. In the next few blogs, I’ll start to describe how we’re trying to make it easy (there’s tons of good work at Intel on this).
When I first started writing this entry, I intended to write about applications and the programming models that work for them. I found myself bogged down in explaining differences in parallel programming models. The problem with trying to characterize a particular application as being dominated by one flavor of parallelism or another is that these types of parallelism are themselves not orthogonal. It’s easy to confuse how parallelism is implemented and how it is expressed (i.e. how the programmer writes it down). Sometimes, it is easier to express parallelism in one style, but have it implemented as another. One way of looking at it is that you want applications to drive how programmers express parallelism and the underlying hardware driving how it’s implemented.
A case in point is our research project Ct, which is nominally a data parallel programming model but is implemented as a bunch of fine-grained tasks and synchronizations (I’ll describe Ct more in a later blog). I often think of parallel algorithms as beautiful crystalline structures comprised of little tasks, data flow and synchronizations. Depending on which facet you look through at the algorithm, it can look “data” parallel, “task” parallel, or one of the many other qualified parallelisms.
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tagged: data parallel, programming models, task parallel, terascale
posted by Sean Koehl on August 14, 2007
This week we are excited to share further technical progress towards our vision to enable scalable, programmable multi-core architectures based on many cores. We are disclosing 8 technical papers from our Tera-scale program via the Intel Technology Journal with new results, key findings, and details on how we expect future architectures with simplified parallel programming models will evolve.
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tagged: applications, benchmark, Intel, model-based computing, multi-core, parallel programming, run-times, task scheduling, terascale, workloads
posted by Ansheng Liu on August 08, 2007
First of all, I’d like to thank every one for sending their comments to my blog “Announcing 40 Gb/s silicon optical modulator.” I will take this opportunity to try to address some of the issues raised in your comments.
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tagged: 40G, modulator, research, silicon, silicon photonics, terascale
posted by Anwar Ghuloum (葛安华) on August 03, 2007
One of the challenges of multi-core and tera-scale architecture is how to make parallel programming “easier”. But what makes it hard in the first place? I thought it might be worth explaining some of our experiences with this as a prelude to explaining how we’re solving it. I’ve ranked things that make parallel programming hard in roughly increasing order of difficulty: 1. Finding The Parallelism 2. Avoiding The Bugs 3. Tuning Performance 4. Future Proofing 5. Using Modern Programming Methods
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tagged: bugs, parallel programming, software development, terascale
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