By John Du, reposted from our Chinese language blog. In my past posts, I’ve talked about Tera-scale computing. Intel has been doing research in both software and hardware on future processor platforms with 10s to 100s of cores. Our objective … Continue reading →

As an editor of the Research@Intel blog, I sometimes have the opportunity to share a guest post to complement those coming from our regular bloggers. Today’s post comes from Mike Mayberry of Intel’s Technology & Manufacturing Group. Mike is Director … Continue reading →

In my last blog, I described why parallel programming is hard. In the next few blogs, I’ll start to describe how we’re trying to make it easy (there’s tons of good work at Intel on this). When I first started … Continue reading →

This week we are excited to share further technical progress towards our vision to enable scalable, programmable multi-core architectures based on many cores. We are disclosing 8 technical papers from our Tera-scale program via the Intel Technology Journal with new … Continue reading →

First of all, I’d like to thank every one for sending their comments to my blog “Announcing 40 Gb/s silicon optical modulator.” I will take this opportunity to try to address some of the issues raised in your comments.

One of the challenges of multi-core and tera-scale architecture is how to make parallel programming “easier”. But what makes it hard in the first place? I thought it might be worth explaining some of our experiences with this as a … Continue reading →