Wouldn’t you like an app that scours a multitude of online resources to connect your college-bound child with the right scholarships and grants? That consolidates the best options for after-school activities across your city for a younger child that fits with your schedule and budget? Or, perhaps one that helps you quickly cut through red tape to secure the best resources to care for an aging relative?

Read more in my blog at hackforchange.org.

Genomics is exciting because it offers the potential to assess your risk of contracting a disease by comparing characteristics expressed by your own DNA to patterns found in others. Admittedly, I’m not certain I want to know what fate may have in store for me. But I would want to know as much as I could about my parents, my wife, or my children, so we could be actively searching for warning signs and take the quickest possible action when and if the time comes.

In a recent ISTC blog, MIT’s Manasi Vartak noted that it is now possible at a single facility to gene sequence more than 2000 people per day, creating about six trillion bytes of data in the process. To understand patterns of gene expression one must look across samples from many people, further compounding the Big Data challenge. It is becoming too much for today’s computing systems. According to Ketan Paranjape, Intel’s Global Director of Healthcare and Life Sciences, as we approach the $1000 per genome mark, downstream analytics and a final diagnosis still costs somewhere in the $100K-$300K range. New applications, tools and compute paradigms are needed to make this more affordable.

One major challenge for genomics, as with many Big Data applications, is a lack of standard benchmarks – a set of algorithms that represent an application’s technical needs. Researchers and computer architects need these benchmarks to test new approaches and to compare results with those of their peers.

Manasi and the MIT Database Group are working with our Parallel Computing Lab (led by Pradeep Dubey), Novartis, and the Broad Institute to publish “GenMark” this fall. This new benchmark suite will represent common genomics tasks such as:

• Given the expression of certain genes, predict the expression of other genes         
• Find genes that behave similarly in the context of a specific disease (aka biclustering)
• Simplifying complex genetic models to a smaller number of key genes (aka SVD)
• Find genes whose expressions are correlated in certain diseases (aka covariance)

Building better systems that can find these correlations among greater populations of genetic data will yield actionable knowledge that doctors can use to guide testing and treatment.

Additionally, Ketan is leading a cross-Intel initiative called “Compute for Personalized Medicine” to help identify and solve the affordability challenges in genomics. He believes that the entire patient ecosystem comprised of the payer (insurance companies, government), provider (hospitals, clinics), pharmaceutical industry and the patient themselves must collaborate across these multiple silos to realize the vision of precision medicine. I look forward to a day when we can apply this knowledge to eliminate as many surprises and lost treatment opportunities as possible.

The ability to exchange and analyze information online has inspired us to digitize everything at a maddening pace — from our music and books to business transactions, scientific data, medical records and much more. Many refer to this as Big Data due to the sheer volume and speed of this digital tsunami.

What we have also found is that data can work wonders. Big Data allows us to take a broader view of the world, find hidden secrets, and fill in pieces of the puzzle that could never be found in smaller, separate datasets. This has taught us something essential: that data holds tremendous socioeconomic value which only increases as the relationships among data are uncovered. One day, the most valuable asset that many institutions – and individuals – will possess will be their data.

Although experts are mining vast amounts of Big Data as we speak, today’s technology struggles to realize its full potential. And very soon we will have much, much more of these valuable bits and bytes with the development of new sensors, wearable technologies, smart grids, smart cities – the emerging Internet of Everything.

As a Technology Evangelist, I have the opportunity to speak to visionary thinkers and technical experts across Intel Labs. From my discussions with our anthropologists I’ve come to appreciate true worth of our personal data. When analyzed, compared, and combined with other data, it can actively work for you — finding new opportunities, discovering personal insights, and connecting you to interesting people.

Intel Labs has a broad collection of research projects driven by the common principal that data is the currency of the future – including work the of future personal data economy, quantified self, graph analytics, data use controls, scalable algorithms, and silicon photonics. We do this through internal research and university collaborations such as the Big Data ISTC centered at MIT. Taken as a whole, we are looking across the full lifecycle of data, from its generation and protection through its analysis and the ultimate experience for the user.

Our Big Data researchers aim to ensure that all of the technologies are in place to provide the foundation for new applications based on massive and/or rapid streams of information. At the same time, our new “Data Economy” initiative (see wethedata.org, one product of this work) looks forward to new opportunities around the exchange of personal information: building use controls directly into data, inventing intelligent agents to perform data exchanges and knowledge discovery, and creating a new digital marketplace in which “data in motion” actively negotiates on your behalf.  

The mining and extraction of these vast new data sources will be akin to a global Gold Rush. By working together to foster the development of a new data economy, wherein individuals and institutions alike can buy, sell, or freely exchange data, wherein everyone has the tools to draw valuable knowledge and insights from their information, and wherein you can protect & control how your data is used – we could create an exciting new data society.

A significant number of people today are collecting and analyzing information on their health, exercise, activities and moods in order to learn things about their life. According to a study by the Pew Research Center, 69% of U.S. adults keep track of at least one personal heath indicator, including 12% who tracked on behalf of a loved one. However, according to the same study only 21% of trackers use technology to do so.  

As the size of computing continues to shrink, more sophisticated wearable devices (e.g. pedometers) will facilitate this data collection as they become more personalized and connected. More analytical tools are also becoming available to allow people to make sense of the data. For instance, one might learn:

• When and what to eat to achieve the best performance in a marathon
• Which foods consistently lead to a depressed or irritable mood
• What patterns at work result in the most productive bursts of activity  

This increased interest in self-tracking has developed into the Quantified Self (QS) movement which aims is to make it easier for people to track the information – or data – in their daily lives (e.g. diet, air quality, mood, blood oxygen levels, etc.) and from this information this derive personal meaning. It’s part of what we call the future “data economy,” wherein people will be able to make their own data work for them, unlocking new insights and opportunities.  

QS has begun to get media attention as well, but more often than not the participants have been wrongly painted in an unfavorable light as narcissists on the fringes of society. Intel Labs ethnographer Dawn Nafus, our resident expert on this movement, challenges this view in a recent post to the official blog of the Committee on the Anthropology of Science, Technology, and Computing (CASTAC). In the blog, Dawn and her collaborator Jamie Sherman explain the motivations and challenges faced by this community as they struggle to get the right data from off-the-shelf sensors to better understand how to do things like maintain good fitness habits or just get a good night’s sleep. They argue that what appears to be egocentric behavior or gratuitous “geeking out” is really just symptom of people trying to make the best of our society’s inclination to try to make one-size-fit-all in terms of solutions for wellness.

Traditional heath regimens are often based on broad studies that statistically average out important person-to-person variations. What people really need, ultimately, is a better relationship with that data.  This could take the form of personalized health care, i.e. recommendations that take individuality into account like genome, health history, and lifestyle.  It could also take the form of self-discovery. Data can help us to understand things about our lives that no one else might think to investigate. What gives me energy? What triggers my allergies? These are matters of personal context, and data can help us decide what daily patterns should (or should not) be changed. Far from a fringe, the QS members are at the leading edge of our future data society. They are trying to understand how to collect and make sense of data in way that works for them – and ultimately you.

Having participated in a QS-style experiment, I can vouch firsthand for the kinds of insights you can get from personal data. I learned, for instance, that the low-stress profile produced during mediation was very similar to that produced while jogging or when listening to a particular song (“Roads” by Portishead). This made me realize that I had multiple options available when I need to de-clutter my mind after a stressful day.

Intel Labs recognizes that your own data will become one of your most valuable assets. In order to foster this new data economy that allows a wider range of people to exchange benefit from such information (and control who it is shared with), Intel is conducting research to develop new innovations which support many citizen science movements, including QS. We’ll be sharing more developments in this and other aspects of our future data society over the coming months.

With the advent of cloud technologies we now have the capability to stay connected from anywhere, anytime. With the recent changes in my family I want to stay connected, attend conferences, have meetings that are as effective as meeting face to face. I don’t want to miss a piece in the action just because I am not on campus or collaborating from a remote location. I know I am not asking for something impossible. With the current tools my workplace provides I can achieve what I want and still remain remote.

 BUT what happens to those organizations that need to plan large and costly training camps or disaster drills, or just fund employee travel and training hours to prepare them for critical situations in the real world? 

Think U.S. Army, or first responder teams dealing with natural disasters. I cannot imagine the consequences if a soldier or a first responder are unable to react and make right decisions when it really counts due to lack of training. So now the question arises in my mind if I can use the existing technologies such as virtual worlds for tactical and procedure training, for fast prototyping of training scenarios, and for large scale mission rehearsals/drills. Unfortunately, the answer I found was that it is not possible because of scalability and realism restrictions. For example, the U.S. Army Research Lab was constrained in their use of virtual worlds only for scenarios with a small unit of personnel (typically less than 20 people).

 So, Intel Labs decided to team up with U.S. Army Research Lab, to prove more complicated missions and a broader set of training applications could be exercised if virtual worlds provide adequate scalability and simulation realism. See the announcement by clicking here.

Intel Labs has developed technologies to support hundreds of participants to interact in a realistic virtual environment so that Army Research Lab can execute on their goal to provide realistic, immersive mission rehearsal exercises.

 Actually, I have a chance to participate in this exercise on March 22^nd, 2013 from 3PM to 5PM PST. This exercise is the first step to prove and demonstrate more than 100 users can operate in the same space at the same time to achieve a realistic mission. I am excited to jump into the virtual environment and interact with other players. See here for details about how to join.

So now when this improvement hits the virtual environment platforms it can be applied to numerous workloads ranging from business to fun play. So now I can stay at home to address my family needs and attend to business.

See here for sample of the virtual environment

With everything being Internet and Cloud, in near future I can envision everything and anything can be put on cloud and be accessible anytime, anywhere. What if your computer screen (aka display) becomes a resource that can be discovered over the internet and be added to the things you see. And what if you can merge multiple source computers to that view? Sounds like multiple remote desktop connections correct? But no, this third eye view provides you a view more than what an remote desktop session can show you. It’s seeing displays from multiple source computers in real time not as separate windows but in the same screen without any lines/borders. That’s a powerful view and the capabilities are endless. Few instances:

In my home I would love to have my third eye view to be shown on my living room TV. I would call this as a family wall. On this wall, I can in real time see what’s happening on the 4 family members’ devices. I can share the pictures I took on my device with my husband at work and watch him edit in his favorite app until I am satisfied. At the same time I can watch my children’s assignments and work on family’s to-do list just like below:

Another instance, all family members can participate in fun family games that includes their individual electronic devices. The challenge for the family members is to not only create a drawing that works on its own, but also as a whole. In other words what they’ve drawn at the edges of their screen need to line up with the edges of their neighboring screen similar to how an Exquisite Corpse works.

For more immersive experience while we are on the go in a camping trip, I can just stack all mobile devices of the family members to form a square and I can suddenly span the movie I was watching on just my device to all 4 devices or 5 devices like below. In this third eye view the video is so perfectly synchronized that it looks like one single large display.

Tell me more what would you do with this third eye view?

To address this growing challenge, Intel Labs today announced the formation of the Intel Strategic Research Alliance (ISRA) for Energy-Efficient Security for SoC devices in Brazil.  The focus of this research effort is to explore the implications of power constraints on the design and implementation of security in SoC devices. Power constraints in most SoC-based devices follow from their reliance on finite lifetime batteries which, when depleted, will terminate the device’s operation. Security solutions (e.g. data encryption) significantly increase the processing requirements of the device and have, in general, become more computationally demanding as security algorithms have evolved to become more robust and as data requirements have sharply increased. Meanwhile, capacity gains in battery technology have increased only incrementally over the years. The result is the well-known battery gap between security solution requirements and available power capacity.

While previous work on lightweight security solutions broadly address the problem of constrained hardware resources in SoC-based devices, Intel believes that much more can be done to design and optimize security solutions specifically for energy efficiency.  For example:

• Minimizing power requirements in security algorithms often leads to a different set of design and optimization decisions.
• Awareness of power management features in the underlying hardware platform can figure in to the design of security algorithms and solutions.
• Security solutions can exploit context-specific information to improve implementation efficiency without compromising robustness.
• The cloud context of many SoC devices leads to additional strategies for power reduction in security solutions.

The goals of this Alliance are:

1. Demonstrate approach feasibility for a constrained SoC energy budget (x) or a range of energy budgets (x, 1.1x, 1.2x, …) associated with future SoC devices.

2. The energy overhead costs of using the approach remains within 10-15% of the overall SoC device energy budget.

3. For those approaches providing alternatives to standard or established approaches, 10-100x reduction in required energy under average operating conditions.

4. Sufficiently robust for application-specific requirements and operational conditions.

The universities participating in the alliance and their areas of focus are as follows:

• University of Sao Paulo – asymmetric cryptography for embedded systems
• University of Brasilia – security protocols based on physical unclonable functions
• University of Campinas – software implementation of cryptographic algorithms
• Pontificia Universidade Catolica do Parana – energy-efficient anomaly detecting
• Universidade Technologica Federal do Parana – energy-efficient anomaly detecting
• Universidade Federal do Parana – energy-efficient anomaly detecting
• Federal University of Minas Gerais – energy-efficient tracking of information flow in SoCs

Which brings me back to why this is a seriously exciting event for me.  With our product teams doing the heavy lifting of making the Hadoop framework less rigid and easier to use while keeping it inexpensive, Intel Labs gets a landing zone for some cool disruptive technologies. In December, I blogged about the launch of our open source scalable graph construction library for Hadoop, called Intel® Graph Builder for Apache Hadoop software (f.k.a. GraphBuilder), and explained how it makes it easy to construct large scale graphs for machine learning and data mining. These structures can yield insights from relationships hidden within a wide range of big data sources, from social media and business analytics to medicine and e-science. Today I’ll delve a bit more into Graph Builder technology and introduce the Intel® Active Tuner for Apache Hadoop software, an auto-tuner that uses Artificial Intelligence (AI) to configure Hadoop for optimal performance.  Both technologies will be available in the Intel Distribution.

So, Intel® Graph Builder leverages Hadoop MapReduce to turn large unstructured (or semi-structured) datasets into structured output in graph form.  This kind of graph may be mined using graph search of the sort that Facebook recently announced.  Many companies would like construct such graphs out of unstructured datasets and Graph Builder makes it possible.  Beyond search, analysis may be applied to an entire graph to answer questions of the type shown in the figure below.  The analysis may be performed using distributed algorithms implemented in frameworks like GraphLab, which I also discussed in my previous post.

Intel® Graph Builder performs extract, transform, and load operations, terms borrowed from databases and data warehousing.  And, it does so at Hadoop MapReduce scale.  Text is parsed and tokenized to extract interesting features.  These operations are described in a short map-reduce program written by the data scientist.  This program also defines when two vertices (i.e., features) in the graph are related by an edge.  The rule is applied repeatedly to form the graph’s topology (i.e., the pattern of edge relationships between vertices), which is stored via the library.  In addition, most applications require that additional tabulated information, or “network information,” be associated with each vertex/edge and the library provides a number of distributed algorithms for these tabulations.

At this point, we have a large-scale graph ready for HDFS, HBase, or another distributed store.  But we need to do a few more things to ensure that queries and computations on the graph will scale up nicely, like:

• Cleaning the graph’s structure and checking that it is reasonable
• Compressing the graph and network information to conserve cluster resources
• Partitioning the graph in a way that will minimize cluster communications while load balancing computational effort

The Intel Graph Builder library provides efficient distributed algorithms for all of the above, and more, so that data scientists can spend more of their time analyzing data and less of their time preparing it.  Enough said. The library will be included in the Intel Distribution shortly and we look forward to your feedback.  We are constantly on the hunt for new features as we look to the future of big data.

Whereas Intel® Graph Builder was developed to simplify the programming of emerging applications, Intel® Active Tuner was developed to simplify the deployment of today’s applications by automating the selection of configuration settings that will result in optimal cluster performance. In fact, we initially codenamed this technology “Gunther,” after a well-known circus elephant trainer, because of its ability to train Hadoop to run faster .  It’s cruelty-free to boot, I promise.  Anyway, many Hadoop configuration parameters need to be tuned for the characteristics of each particular application, such as web search, medical image analysis, audio feature analysis, fraud detection, semantic analysis, etc.  This tuning significantly reduces both job execution and query time but is time consuming and requires domain expertise. If you use Hadoop you know that the common practice is to tune it up using rule-of-thumb settings published by industry leaders.  But these recommendations are too general and fail to capture the specific requirements of a given application and cluster resource constraints.  Enter the Active Tuner.

Intel® Active Tuner implements a search engine that uses a small number of representative jobs to identify the best configuration from among millions or billions of possible Hadoop configurations.  It uses a form of AI known as a genetic algorithm to search out the best settings for the number of maps, buffer sizes, compression settings, etc., constantly striving to derive better settings by combining those from pairs of trials that show the most promise (this is where the genetic part comes in) and deriving future trials from these new combinations.  And, the Active Tuner can do this faster and more effectively than a human can using the rules-of-thumb.  It can be controlled from a slick GUI in the new Intel Manager for Apache Hadoop, so take it for a test run when you pick up a copy of the Intel Distribution.  You may see your cluster performance improve by up to 30% without any hassle.

To wrap, these are one-of-a-kind technologies that I think you’ll have fun playing with.  And, despite offering quite a lot, Intel® Graph Builder and Intel® Active Tuner are just the beginning.  I am very excited by what’s coming next.  Intel is moving to unlock the power of Big Data and Intel Labs is preparing to blow it wide open.

*Other names and brands may be claimed as the property of others

At ISSCC 2013, Mozhgan Mansuri of Intel Labs is presenting paper describing chip-to-chip I/O that combines extremely high (terabit per second) data rates, world-class energy efficiency, and the capability to rapidly tune performance vs. power consumption to use the minimum energy at any given time.

As Intel continues to drive Moore’s law and increase the processing capabilities of products such as Xeon and Xeon Phi, many data-intensive applications may become limited not by the processor, but by how fast you can “feed the beast” by moving massive amounts of data between processors or between processors and memory. This work represents the latest advancement to address this issue from our Electronic Signaling Research team led by Bryan Casper.

Mozhgan’s paper details a research prototype capable of moving a total of 1 trillion bits of data per second across a 50cm I/O link (combining the data moving in each direction) while consuming only 2.7 Watts of power. To put a terabit/s in perspective, this speed would be enough to transmit the following in 1 second:

• Two seasons of a TV drama in 720p HD
• The contents of a 100GB laptop hard drive
• An entire music library of 150+ albums

Novel I/O circuits are used to transmit and receive data across a ribbon composed of thin “micro-twinax” cables attached directly to the processor or memory packages with a high-density connector. The ribbon link consists of 32 parallel I/O channels in each direction, each capable of sending 16 Gigabits per second.

The circuits can rapidly tune to lower data rates of 8, 4, or 2 Gbps per channel when needed, further increasing power efficiency by up to 3x. As such, the link can operate a total data rate of 256 Gbps while consuming just over 200 milliwatts of power.

An additional feature is redundant I/O channels to increase link reliability. The extreme density allowed for 4 extra channels in each direction. In practice the link could be tested and configured to use the best 32 of the 36 physical channels.

While still in the research phase, this achievement represents the most dense I/O ever achieved over copper wiring in terms of data transmitted per unit area. Compared to other recently reported results on similar high-bandwidth links, this works represents the best power efficiency at twice the data rate – and at longer link distances. It’s an important step towards enabling future data intensive applications.

Imagine an SUV that transforms into a motorcycle at the push of a button.  When lugging around the family or car full of friends, you’d use the SUV option.   When driving solo, you’d save on gas by pushing the button and taking a motorcycle.   You’d have the power and capacity of the SUV when you need it and the fuel efficiency of the motorcycle when you don’t.  Similarly, to maximize battery life in today’s mobile devices, it’s critical that each task performed on the system is completed with the right resources.   Our CPUs should be small and efficient when performing lightweight tasks such as chatting or messaging, but also offer the performance headroom required for heavier workloads such as video and image processing. 

Although we may be a long way from implementing technology like this in our cars, recent research shows promising results for CPUs, indicating a potential for 10% performance gains and 22% better energy efficiency.  In fact, a recent collaboration between Intel Labs and the University of Texas (UT) has won acclaim for its approach to this problem.   

Intel Labs University Research Office has been working with an international team of researchers at universities such as UT, Carnegie Mellon, NC State and the American University of Beirut.  This collaboration hopes to develop designs that can configure themselves for a wide range of workloads, scaling down for lightweight tasks, and scaling up to maximize performance for heavyweight tasks.   In addition to providing funding, Intel encourages engineers to work closely with students and faculty at the universities to maximize the exchange of ideas.  This approach to research has started to bear fruit.  The collaboration between Intel and Professor Yale Patt and his HPS Research Group at The University of Texas resulted in the development of MorphCore, a CPU that “morphs” between two configurations.  One configuration tailored for high performance single-threaded workloads, and a second for higher throughput multi-threaded workloads.   At the 2012 International Symposium on Microarchitecture this work received the “best paper” award for its “conceptual novelty and anticipated long term impact”. 

To better understand how this works, recall that maximizing single thread performance requires high performance CPUs to allocate all available resources to the currently running thread.  In particular, single thread performance depends on large register files that re-order instructions, allowing them to execute just-in-time rather than forcing them to wait for preceding instructions.  In contrast, when concurrently executing several threads, it’s often more efficient for the CPU to delay work on a stalled thread, focusing instead on other threads.   In this mode, buffers that allow instruction re-ordering don’t improve performance, and may even reduce efficiency by continuing to consume power.   

UT’s MorphCore addresses this problem by modifying the design of a high performance CPU to permit shutting down some buffers and repurposing others.   Throughput mode splits the largest of these structures, the physical register file (PRF), into equal partitions, each storing the architectural state of one executing thread.   This dramatically simplifies renaming, which assigns buffer space for fetched instructions.    In addition, throughput mode turns off the load buffer and much of the store buffer, sacrificing memory reordering in favor of reduced power.  With optimizations explored so far, MorphCore simulations show 10% performance improvements as well as energy efficiency (Energy^2*Delay) gains of 22% versus a traditional high performance CPU.  With these and other promising ideas developed in collaboration with Intel’s academic partners, processors in the next 5-10 years may offer the best of both worlds: high performance to minimize delay and deliver the best user experience; as well as throughput mode to maximize efficiency when single thread performance is less important.

UPDATE 2/5/2013: Added a reference above to Professor Yale Patt and his group at UT.

But Big Data does have structure; it just needs to be discovered from within the raw text, images, video, sensor data, etc., that comprise it.  And, companies, led by pioneers like Google, have been doing this for the better part of a decade, using applications that churn through the information using data-parallel processing and convenient frameworks for it, like Hadoop MapReduce.  Their systems chop the incoming data into slices, farm it out to masses of machines, which subsequently filter it, order it, sum it, transform it, and do just about anything you’d want to do with it, within the practical limits of the readily available frameworks.

But until recently, only the wizards of Big Data were able to rapidly extract knowledge from a different type of structure within the data, a type that is best modeled by tree or graph structures.  Imagine the pattern of hyperlinks connecting Wikipedia pages or the connections between Tweeters and Followers on Twitter.  In these models, a line is drawn between two bits of information if they are related to each other in some way.  The nature of the connection can be less obvious than in these examples and made specifically to serve a particular algorithm.  For example, a popular form of machine learning called Latent Dirichlet Allocation (a mouthful, I know) can create “word clouds” of topics in a set of documents without being told the topics in advance. All it needs is a graph that connects word occurrences to the filenames.  Another algorithm can accurately guess the type of noun (i.e., person, place, or thing) if given a graph that connects noun phrases to surrounding context phrases.

Many of these graphs are very large, with tens of billions of vertices (i.e., things being related) and hundreds of billions of edges (i.e., the relationships).  And, many that model natural phenomena possess power-law degree distributions, meaning that many vertices connect to a handful of others, but a few may have edges to a substantial portion of the vertices.  For instance, a graph of Twitter relationships would show that many people only have a few dozen followers while only a handful of celebrities have millions. This is all very problematic for parallel computation in general and MapReduce in particular.  As a result, Carlos Guestrin and his crack team at the University of Washington in Seattle have developed a new framework, called GraphLab, that is specifically designed for graph-based parallel machine learning.  In many cases, GraphLab can process such graphs 20-50X faster than Hadoop MapReduce.  Learn more about their exciting work here.

Carlos is a member of the Intel Science and Technology Center for Cloud Computing, and we started working with him on graph-based machine learning and data mining challenges in 2011.  Quickly it became clear that no one had a good story about how to construct large-scale graphs that frameworks like GraphLab could digest.  His team was constantly writing scripts to construct different graphs from various unstructured data sources.  These scripts ran on a single machine and would take a very long time to execute.  Essentially, they were using a labor-intensive, low-performance method to feed information to their elegant high-performance GraphLab framework.  This simply would not do.

Scanning the environment, we identified a more general hole in the open source ecosystem: A number of systems were out there to process, store, visualize, and mine graphs but, surprisingly, not to construct them from unstructured sources.  So, we set out to develop a demo of a scalable graph construction library for Hadoop.  Yes, for Hadoop.  Hadoop is not good for graph-based machine learning but graph construction is another story.  This work became GraphBuilder, which was demonstrated in July at the First GraphLab Workshop on Large-Scale Machine Learning and open sourced this week at 01.org (under Apache 2.0 licensing).

GraphBuilder not only constructs large-scale graphs fast but also offloads many of the complexities of graph construction, including graph formation, cleaning, compression, partitioning, and serialization.  This makes it easy for just about anyone to build graphs for interesting research and commercial applications.  In fact, GraphBuilder makes it possible for a Java programmer to build an internet-scale graph for PageRank in about 100 lines of code and a Wikipedia-sized graph for LDA in about 130.

This is only the beginning for GraphBuilder but it has already made a lot of connections.  We will continually update it with new capabilities, so please try it out and let us know if you’d value something in particular.  And, let us know if you’ve got an interesting graph problem for us to grind through.  We are always looking for new revelations.

This February, a new documentary about the rise of Silicon Valley and the story of Bob Noyce will air on the Public Broadcasting System’s American Experience, the most-watched history series on American television.

As the filmmakers put it, the radical innovations of the brilliant, charismatic young physicist Noyce included the integrated circuit, which transformed the way the world works, plays, and communicates, and has made possible everything from space exploration to smart phones, pacemakers to microwaves. In other words, all of modern electronics and, directly or indirectly, most of modern technology.

A quote from Bob guards the entrance to the Robert Noyce Building: “Innovation is everything.”

Hasn’t innovation moved on to someplace else? Like consumer electronics, e-readers, phones, tablets – all the cool gadgets in the Top Ten Black Friday Most Popular Items list?

You could be forgiven for having missed it, or for thinking it didn’t matter much: Recently the IEEE named two retired Intel technologists, Sunlin Chou and Youssef El-Mansy, the next winners of its Robert N. Noyce Medal.

All Chou and El-Mansy did was this: Establish a research-development manufacturing methodology that led to industry leadership in logic technology for advanced microprocessor products. And that led to strained silicon at 90 nanometers, high-k and metal gate at 45nm, and tri-gate transistors at 22nm. Along the way, organizational innovations from Chou and El-Mansy included Copy Exactly, a focus on defect reduction, increased work-in-process turns, and more.

Andy Grove, in an email to them, wrote: “Bob Noyce, who knew a thing or two about exceptional contributions, would be even more emphatic in congratulating you. But what makes me even more proud and awestruck is how you have done all this, generation after generation, like clockwork, with no histrionics, just focusing on the science, the discipline, the taking of reasoned risk – all the things Intel has been about. I salute the two of you and the thousands who helped you.”

Andy Bryant said: “They are a big part of what made Intel Intel. They were that good. What they accomplished was remarkable.”

In America’s revolutionary 1960s, when antiwar demonstrations, student protests on college campuses, and the Free Speech movement at UC Berkeley held society’s attention, Gordon Moore famously commented that he thought the people in this industry, those working in labs and fabs, were the real revolutionaries. They saw they were changing a lot of the way the world was going to operate.

Bob’s partner in Fairchild and Intel, Gordon; other Fairchild colleagues such as Jean Hoerni, whose planar process made ICs happen; the young Hungarian émigrés Andy Grove and Les Vadasz – who followed Bob and Gordon to get Intel off the ground – were but the first in a string of world-class scientists and engineers who created, nurtured, preserved, and advanced the technology defined by Moore’s Law.

But this is just history, right? Is this really relevant? Now?  

Fifty years since the small band of revolutionaries at Fairchild set out on this path, Intel is stuffed with such world class technologists. Who else could have carried us here? Youssef retired in 2004, and Sunlin left in 2005. The heartbeat stays strong.

Sunlin and Youssef were simply the best in a crucial era.

In any era, whether the eras of the first ICs, the first microchips, the first microprocessor, or today, what Grove said about the two awardees –generation after generation, like clockwork, no histrionics, focusing on the science and the discipline, taking reasoned risk – is what Intel, its founders, and its current generation of innovators are all about.

It’s not all in the history books yet; those are still being written. It is the future as well. The work of Chou and El-Mansy perfectly continued the legacy of Bob Noyce. And, like Noyce’s amazing contributions, it lights the way to the story of the future.

Radar imaging can do both of these by probing the earth with radio waves and using a computer to process and render their echoes as a picture. This imaging technique provides information about the materials on or just below the surface of the earth. Such an approach is the subject of a paper at SC12 this week.

This has practical applications beyond the obvious military ones, such as for:

• Monitoring crop characteristics for farmers
• Revealing ice hazards for ocean navigation
• Geology and mineral exploration
• Environmental monitoring of deforestation or oil spills
• Providing aircraft autopilots with real-time, all-weather images of the terrain ahead

The challenge with radar imaging is that due to the nature of radio waves, the aperture size required to collect the image is many meters – very large compared to a telescope lens, and not at all portable. Instead, a large aperture is synthesized by flying a plane-mounted radar system in a circular pattern and combining all the data into one image. This technique is called “synthetic aperture radar” or SAR.

In order to make SAR capabilities available for the civilian applications listed, two challenges must be addressed. First, creating a SAR image is computationally intense, requiring 100s of Teraflops processing power. Second, the collection algorithms typically used require that the surface to be imaged be very flat and the plane’s flight path to be nearly perfect, inducing many practical challenges.

Intel is presenting a paper at SC12 that tackles both problems successfully. Intel Labs and Intel’s Software & Services Group (SSG), in collaboration with Georgia Institute of Technology demonstrate the potential for significant reductions in computational cost using a ‘backprojection’ algorithm. Backprojection is a SAR imaging technique that allows non-flat surfaces to be imaged with more flexible flight paths – i.e. without having to fly in an absolutely perfect circle. However, backprojection has been considered less computationally efficient. Intel Labs and SSG demonstrate that through algorithmic innovation and parallel processing using Intel® Xeon® systems equipped with the new Intel® Xeon Phi™ co-processor (two per node), over 35 billion SAR backprojection calculations per second can be performed. This is enough to generate the equivalent of one 3000 x 3000 pixel image per second per compute node. The addition of Xeon Phi cards sped each node by 4.8x for this application (see notices below).

Furthermore, these algorithmic improvements have the potential to be applied to imaging applications in a variety of other fields. The backprojection method is similar to those used in medical applications such as X-ray CT scans and ultrasound imaging. Hence this research could help advance imaging capability for a variety of data-intensive image processing applications.

Legal Notices:

• Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products.  For more information go to http://www.intel.com/performance
• Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.  Notice revision #20110804

Numerous wave applications (e.g. sound, radio) rely on the Fast Fourier Transform (FFT) including signal processing, communications, and multi-media. However, it is a very challenging problem to parallelize effectively. This is because for big FFT datasets running on large clusters, 50%-90% of time can be spent waiting on node-node data transfers rather than useful calculation.

Intel’s Software and Services Group & Intel Labs devised a new framework for distributed 1-D FFT problems which traditionally require three costly all-to-all inter-node data exchanges. The new approach delivers multiple 1D FFT algorithms requiring just a single all-to-all inter-node data exchange. According to the research, for large-scale problems this can double FFT performance (see the paper for details). Another key feature is that users can opt to further increase FFT performance by accepting reduced-accuracy results, so the algorithms scale to fit the needs of the particular application.

The answer may lie in Big Data — the ability to simultaneously correlate the movements of vast numbers of galaxies and find patterns that unlock these darkest of secrets in the universe. The challenge is keeping up with the data. In recent decades, the observed and simulated datasets have grown from a few dozen objects to billions. With the advent of bigger and faster telescopes there is no end in sight for the exploding data. Performing the necessary algorithm (called the Two Point Correlation Function or TPCF) today on a billion galaxies would take a single processor 50 years to analyze — and even today’s supercomputers are hard pressed to keep up. The computational requirements are expected to grow further, well into the domain of Exascale computing. This is the subject of an ACM Gordon Bell Prize – nominated SC12 paper from Intel this week.

Intel Labs, in collaboration with Lawrence Berkeley National Laboratory (LBNL) and the University of California, Berkeley (and in support of their ISAAC project) has demonstrated new techniques to significantly accelerate the computation of TPCF on these immense datasets and reduce both the cost and energy of the quest of cosmic understanding. This approach is comprised of three components: 1) the ability to effectively distribute and manage the work across tens of thousands of Intel® Xeon® compute cores, 2) more efficient use of the SIMD (single compute on multiple data) capabilities within each Intel Xeon core, and 3) more efficient communications among the compute nodes.

This technique was tested on a 1.7 billion object dataset (provided via a collaboration between LBNL and the University of Sussex) using Lawrence Livermore National Laboratory’s Zin computer, a Petascale-class machine with 1600 nodes each containing two Intel Xeon processors. The calculation was completed in just over five hours — more than 35 times faster than previous approaches (see notices below). This means scientists will be able to use this technique to complete experiments in a single day rather than weeks. In addition, the experiment demonstrated an 11x improvement in cost efficiency (measured in flops/$), making these experiments more practical and affordable.

More recently on the Texas Advanced Computing Center’s Stampede cluster, a Petascale computer using Intel® Xeon Phi™ Coprocessors (launched this week), Intel Labs achieved a further speedup in run-time of 3.2 X on each node in comparison to the results above (see notices below).

This technique provides a path to computing even larger datasets into the Exascale domain, where new answers to many cosmological questions may be found within the next decade.

Legal Notices:

• Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products.  For more information go to http://www.intel.com/performance
• Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.  Notice revision #20110804

Intel Labs White Paper: The Future of Knowledge Work

The record-breaking computer, called Beacon, belongs to our collaborators at the National Institute for Computational Sciences (NICS). NICS is a well-known center in high-performance computing, established in partnership with the University of Tennessee and Oakridge National Lab (ORNL).  Beacon is an appropriate name as it lights the way for future systems by achieving 2.5 billion floating point operations per section for each Watt of power consumed (2.5 Gigaflops/W).

Green500 was established in 2007 and ranks high performance computers in terms of energy efficiency: performance per watt. This increased focus on energy consumption is essential to the future of computing from the tiniest mobile devices to the largest supercomputers. It’s particularly vital to the development of practical Exascale computers over the next decade. This result shows the benefit that a significant increase in general purpose, chip-level parallel processing brings to the table with the 60-core Xeon Phi.

While our team was working on our own Green500 submission, it was not easy to find resources and justification to build a large cluster designed specifically to target energy efficiency.  Dr. Glenn Brook at NICS and team had the resources to design a new supercomputer from ground-up aimed at energy efficiency. Intel had the knowledge of Xeon and Xeon Phi algorithmic optimizations needed to achieve the ambitious goals.

Looking back, the progress has been significant. Just four years ago, the highest ranking Xeon cluster on the Green500 list stood at only 265 Megaflops/W.  Today’s achievement represents nearly a 10-fold improvement for Intel Architecture in just four years. This is the latest step in a long journey towards parallel computing and many-core that began over eight years ago – as described in part 1 of our many-core web documentary.

More importantly, in working round the clock towards this goal the team learned much more in the past few months than they could have otherwise.  They developed significant innovations from algorithms to system hardware designs aimed at energy efficiency. This was a top-down, energy efficiency focused effort to co-design every software-hardware element that mattered.

Pradeep Dubey, our Intel Fellow leading the algorithmic innovations also remarked that “this is the most remarkable collaboration story that I can think of in my Intel career so far.” In addition to the work with NICS, the collaboration spanned many teams within Intel product groups and Intel Labs. The team members were also spread across many time zones.  According to Pradeep, this was “yet another proof point of how we can achieve almost anything if truly passionate people collaborate to complement their skills.”

One can envision these relationships as web of interconnected points. Computers see these webs in the form of a data structure called a ‘graph.’ Real world examples include the network of roads connecting cities in a country, the neural connections in your brain, or the Internet itself. A graph can be created from almost any collection of data, with the connections specifying relationships. On social networks, you see graphs in the form of your networks of friends, families, and colleagues. Mining relationships within big graphs is the subject of an Intel Labs paper presented today at SC12.

The more data you add to a graph, the more potential you have to discover insights that are personally, culturally, or financially valuable. The challenge is that today the datasets are growing faster than compute systems can handle.

Imagine you are mapping out a highway system of an unfamiliar country starting from scratch. Until you get to the next town, you have no idea where the next road will take you. Likewise as a computer searches a graph, going from node to node in the web, it doesn’t know where in memory it will need to look for the next set of nodes. The best way to do this search efficiently is to keep all of the data together in main memory so anything can be readily retrieved.

However, datasets have grown well beyond what can be stored in one computer’s memory. They may require tens, hundreds, or even thousands of computers for applications like cosmology, where the relationships between billions of galaxies are being explored to better understand the evolution and fate of the universe. As such, the next challenge for graph computing is to run across large clusters of computers. Since they span the memory of many systems, searching them means constantly looking for data that resides on another machine. Today, these calculations are severely limited by the amount of information that can flow between the many processors in a cluster at one time.

To help address this, Intel Labs has developed new methods to accelerate the computations of large graphs by reducing the amount of data communication required across the cluster’s networks. As described in the SC12 paper,  this is accomplished though a collection of techniques to efficiently compress data, eliminate unnecessary transfers, and pipeline computations to make the most of time spent waiting for data to return.

The results were demonstrated using the Graph500 benchmark, an emerging benchmark used to rate high performance computing systems on their ability to compute graphs. Through these improvements, Intel Labs showed that these graph searches can be done more than six times faster, and in a way that is more than eight times more energy-efficient.  For both Big Data and HPC this efficiency is critical, as energy and cooling have become major concerns for future datacenters and supercomputers alike.

These results represent one of the most efficient implementations of Graph500 benchmark, based on the most recent list. More efficient computation will make these graph insights more accessible to a wider array of people, business, and scientific institutions.  

 Click here for more information on all six of Intel’s papers at SC12.

On October 23rd the University Program Office at Intel honored 9 faculty and 25 doctoral students from European Union (EU) universities through two new innovative programs – the Early Career Faculty Honor Program (ECFHP) and the Doctoral Student Honor Programme (DSHP). Both of these programs award cash gifts intended to help support research and education as well as to enable the awardees to travel to Intel to collaborate with Intel researchers.

The Intel Early Career Faculty Honor Program targets faculty who are relatively new to academia with less than 4-years of experience.  16 of the top universities in the EU submitted 33 nominations based on innovative research in areas such as sustainability, smart cities, embedded applications and visual computing. These nominees then submitted an application form which was reviewed and rigorously evaluated by committees of Intel’s top researchers. Out of these 33 nominations 9 were selected as being the best. They are as follows:

Intel Early Career Faculty Honorees pose with Intel Representatives, Kimberly Sills and John Somoza

• Esteve Amat of the U. Polit. de Catalunya
• Mélanie Bourocheof Trinity College Dublin
• Chiara Buratti of the University of Bologna
• Christophe Dubach of the  University of Edinburgh
• Andrew Keane of the University College Dublin
• Bastian Leibe of RWTH Aachen
• Jan Reineke of the University of Saarland
• Thomas Schneider of TU Darmstadt
• Vanessa Wood of ETH Zurich

The Intel Doctoral Student Honor Programme awards fellowships to exceptional PhD candidates pursuing leading-edge innovation in fields related to Intel’s business and research interests. The goal of the program is to advance innovation in key areas of technology, as well as develop a pipeline of world-class technical talent for Intel’s future workforce and the global knowledge-based economy.  The selection of this year’s recipients was a highly competitive process with many outstanding quality applicants across several universities and exciting areas of research.  For the 2012-2013 academic cycle, 25 finalists were selected from a pool of 66 applicants across 16 universities.  Congratulations to all of this year’s awardees!

Intel Doctoral Student Programme Honorees pose with Intel Representatives, Kimberly Sills and John Somoza

• Jose Maria Arnau of the U. Polit. De Catalunya
• Jeronimo Castrillon of RWTH Aachen
• Jose David Domenech Gomez of the U. Polit. De Valencia
• Jesus Friginal Lopez of the U. Polit. De Valencia
• Shrikanth Ganapathy of the U. Polit. De Catalunya
• Carmen Garcia of the U. Polit. De Catalunya
• Sven Gehring of Saarland University
• Manuel Gorius of Saarland University
• Alexander Heinecke of TU Munchen
• Alec Jacobson of ETH Zurich
• Gareth Jones of Imperial College London
• Daniel Kelly of Imperial College London
• Pejman Lotfi Kamran of the Ecole Polytechnique Federale de Lausanne
• Pascal Meinerzhagen of the Ecole Polytechnique Federale de Lausanne
• Bojan Milosevic of the University of Bologna
• Bharghava Rajaram of the University of Edinburgh
• Pablo Reble of RWTH Aachen
• Michele Rossi of the University of Bologna
• Lisa Ruttledge of the University College Dublin
• Reinhard Schneider of TU Munchen
• Lars Schor of ETH Zurich
• Aonghus Shortt of the University College Dublin
• Evgeny Strekalovskiy of TU Munchen
• Alejandro Valero of the U. Polit. De Valencia
• Cristian Zamfir of the Ecole Polytechnique Federale de Lausanne

Additional Authorship by: John Somoza

-Justin

SAE Convergence 2012 – Blue Ribbon Panel
Detroit, Michigan October 16th, 2012
Prepared Remarks by Justin Rattner, Intel CTO

While my wife will tell you I’m a car guy, in this crowd I’m strictly an IT guy or should I say an ICT guy, since Intel builds both computers and radios. Suffice it to say, and with apologies to Al Jolson, “folks, you ain’t seen nothing yet.” In-vehicle ICT is really in its adolescence. Let me take my few minutes to whet your appetite for what’s to come. The most exciting development is what many, including Intel, are calling the connected car, and by that I mean a car that is constantly (or almost always) connected to the Internet, and through the Internet, to both cloud-based services and to other vehicles. Connectedness, if I can use that expression, is likely to change the in-vehicle experience as much as anything we’ve seen from the so-called infotainment systems of today. But, nothing in life is free or perfect, so there’s bound to be runs, hits, and plenty of errors.

I cannot overemphasize the importance of getting the in-vehicle experience right from the get-go. Some years ago, a Florida real-estate development featured a speech-driven master control system in every house. When asking the system to turn off the lights often resulted in a long-distance phone call to some distant relative, the developer literally pulled the plug. It’s our responsibility both as vehicle makers and technology suppliers to ensure that what we deliver works flawlessly before it hits the road. Getting the experience right requires new sets of skills, skills that aren’t often taught in engineering school. At Intel we’ve spent a decade building up expertise in areas such as ethnography, anthropology, and the social aspects of computing, to be sure our products comprehend not just what the engineers think is “cool” or “neat” but those qualities of technology that occupants truly enjoy and relate to on a level some would describe as love. Now, that I know they didn’t teach at my engineering school.

Getting the experience right also means improving safety for both the driver and the passengers. Technology doesn’t have to make things harder and more distracting. We know for sure that passwords have to go. You can’t have people trying to type in a different password for every unique in-vehicle service. Biometrics will be essential in authenticating the driver or passengers to the vehicle. Once done, the vehicle can authenticate the occupant to any service. I recently demo’d such a system at the Intel Developer Forum where we used the pattern of blood vessels in your hand to authenticate the user to the platform, which could have been an ultrabook, a smartphone, or a car. Once done, the system quickly authenticates the car to whatever registered services you require. No passwords at all, ever.

Experience-driven design is about to take a very important step into the future. Technologies well along in development will allow the vehicle to become “context aware” which is to say they will know a non-trivial amount of things about the driver and other occupants. That knowledge will only increase as the vehicle is driven, making the car appear smarter over time. Context awareness is based on the fusion of hard sensors, such as geolocation and weather conditions with soft sensors such as your calendar, your contacts, and your social network. All these knowledge sources working together will allow future vehicles to adjust to your driving behaviors, anticipate where you are going without explicit input, and help you manage your life while you are driving. Making sure this information is kept private and secure is an absolute requirement and must be built-in from the get-go.

One thing is for sure, the connected car is going to be a lot smarter and a lot more fun to drive. Simply put: a great personal experience and one that you’ll enjoy again and again. Sounds like love to me.

Intel is pleased to contribute nearly $1M to support the best PhD students across the nation engaged in innovative areas of computing research.  The Intel PhD Fellowship Program is a highly competitive process where students are first pre-selected by their universities to apply for this fellowship. Each student that is nominated by their respective university submits a comprehensive application which is then reviewed by Intel Fellows and senior technologists. Participating academic research institutions and doctoral student candidates consider this fellowship a very prestigious award.  The recipients of this fellowship are all recognized leaders in their field and come very highly recommended by their university and/or industry partners.

The fellowship program was started in the early 90′s by Gordon Moore to recognize and honor top students for their leading edge research in areas that would benefit mankind; it was open to all fields of research. Gordon wanted to give back to those universities and communities who excelled at producing the top students. It was a way to build long lasting relationships with these universities, the professors and help create the next generation of technology leaders. The program has been supported every year for nearly 2 decades. Today’s program keeps that focus and also places an emphasis on developing students who are well aware of issues facing the computing industry. Every winning student is assigned a technical mentor at Intel who is also a leader in their field. Students are encouraged to work through their mentor and develop a deep understanding of the technical issues facing our world and to be on the forefront of solving the technical challenges that lie ahead.

This year, 18 fellowships were awarded. All of the winning students were invited to Intel in Oregon for the PhD Fellowship Forum. During this forum, the students met and heard inspiring messages from top technical leaders across the company including Limor Fix, Mario Paniccia, Ian Young, Kelin Kuhn, Brian David Johnson, and many others. They also attended a networking dinner with many of the speakers as well as other Intel Fellows, Executives and Senior Principal Engineers. Intel is very proud to announce the list of this year’s winners – Congratulations to all!!!

The hands-on activity encouraged beginner Makers of all ages to create simple electronic musical instruments.  Using the conductive properties of simple pencil graphite and the metal clip on a clipboard, visitors to the booth could draw and then play their own unique instruments. Makers, young and old, were encouraged to explore the creative possibilities of this simple system, and while they did, they were exposed to some basic concepts about conductivity, simple circuits, input and output, and the importance of grounding!

The handmade instruments were hooked up to a computer via alligator clips and a Makey Makey kit, with one performance area providing drum sounds and the other a set of synth notes.  Kids and adults rocked out with their custom instruments.  We also provided more advanced materials-conductive paint, copper tape, and aluminum foil-for visitors who wanted to construct bigger, more elaborate instruments. Cardboard guitars proved to be a crowd favorite!

The Intel-hosted  activity was a big hit with Maker Faire visitors, from kids through adults.  OMSI estimates attendance at around 2500-3000 people each of the two days.  Intel invests more than a $100 million a year in science, technology, engineering and math (STEM) programs because a solid math and science foundation coupled with skills such as critical thinking, collaboration, and problem solving are crucial for students’ success.  Sponsoring events like Portland’s first Mini Maker Faire helps encourage the next generation of young Makers and innovators who, Intel believes, are the key to solving our current and future global challenges.

Also present were two booths of “Intel Makers,” Intel employees and their families who have personal, Maker projects that they pursue in their spare time. Tanenbaum Fabrications (Karen Tanenbaum of Intel Labs and her husband, Josh) exhibited their Steampunk art and electronic component jewelry, while Kinetic Creatures (Lucas Ainsworth of Intel Labs and his partner, Alyssa Hamel) showed off their crowd-pleasing mechanical cardboard creatures.

Along with O’Reilly Media, Cognizant and Pixar, Intel is a founding sponsor of the non-profit Maker Education Initiative whose mission is to create more opportunities for young people to make, and, by making, build confidence, foster creativity, and spark interest in science, technology, engineering, math, the arts—and in learning as a whole.  OMSI is also engaging with the Maker movement, working on plans to turn part of their space into a dedicated Makerspace.

1. The games today offered by cloud gaming vendors are just the same as their PC or console versions. However: A powerful cloud could do much more! Three examples (ray tracing, voxel rendering and photo-realistic rendering) are given on what cool improvements could emerge.
2. Latency is a big topic. However the first thought of just focusing on the internet latency is wrong. There are many other sources of latency in the chain which are discussed in detail and suggestions on how to fix those are given.
   
3. Sufficient bandwidth is at least as important. The upcoming boost in screen resolutions could soon be the biggest challenge for cloud gaming.

To make this vision a reality, I along with my team have been working in collaboration with Prof. Paul Utz’s lab at Stanford to further develop and validate a novel silicon-based peptide array platform for biological applications, technology feasibility for which had its origins in then Intel Labs (CTG).  We have perfected and further demonstrated biological utility of this wafer scale, high-density, in-situ peptide array platform made with silicon as a support surface, using maskless photolithography approach to synthesize arrays containing peptides covering disease relevant proteins. The research paper demonstrating proof-of-concept studies for Intel peptide arrays as research tools will be published in the August 19^th issue of Nature Medicine. In this paper we describe the use of peptide arrays containing every possible overlapping peptide within a linear protein sequence of a region of a protein, H2B, which has been shown to be associated with the autoimmune disease systemic lupus erythematosus (SLE). We demonstrate the functionality of these peptide arrays using commercial antibodies against H2B, and used these arrays to study autoantibodies in SLE patients with increased disease severity.

While our current approach employs optical detection, the eventual goal is to integrate the peptide arrays with a complementary metal-oxide semiconductor (CMOS) circuit beneath each peptide feature to enable electronic sensing for increased robustness, cost effectiveness,  and ease of use. This technology has the potential to transform the field by allowing for real-time electronic measurements and computations, which are not possible with current approaches. We have leveraged (already demonstrated by pioneers in case of photolithography based DNA microarrays on glass surfaces) mature semiconductor fabrication technology to create  silicon based  peptide array platform for protein analysis; to potentially enable detection and analysis of multiplex interactions in real time and enable large scale proteomic studies which have been elusive so far.

Use of these chips for example, could aid clinical research and if developed for detection of serum biomarkers, could rival pharmacogenetic analyses to define subsets of patients who would best respond to therapeutic agents. Peptide arrays platform being agnostics can enable wide range of proteomic applications for  epidemiology and population studies beyond medicine, such as  agriculture & animal husbandry, bio-defense, food & beverage testing, monitoring of ecology and environmental parameters.

To address these challenges Intel Corporation brought some of the best visual computing researchers together in 2011 to develop the Intel Science and Technology Center for Visual Computing (ISTC-VC). Researchers from this Center are having an impact in this area. Already they have written 25% of the papers published at SIGGRAPH 2012 describing research that will fundamentally change the nature of visual computing over the next 5 to 10 years. This clearly demonstrates the progress Intel and the researchers at the ISTC are making in visual computing.

Click here to find out more on what Intel has in store at SIGGRAPH 2012.

Imagine being able to adapt your virtual avatar’s’ walking style depending on if it’s walking on a country road vs slippery slope. Imagine being able to see the yarn level details of woven fabrics while shopping in the virtual store with all visually important effects in its modern interior that may include fabrics such as drapes, sofas, wine glass on table with all reflections, clothes etc. and is no different from a store in real world. Last but not the least, hearing realistic life-like sounds resulting from tiny to large object interactions.

The ISTC-VC papers published at SIGGRAPH 2012 also describe research that makes content creation a breeze. ISTC-VC research promises to make it possible for the average user to include characters in their virtual environments that carry out human tasks autonomously – one simply will have to give these characters a goal such as ”move over to the chair and sit down” and the software associated with the character will figure out how to achieve the goal in a natural humanlike fashion.   https://www.box.com/s/d1ed902a25c1ce263195

ISTC-VC research also promises to enable the average computer user to create sophisticated content by manipulating the large amounts of modeling data available on the web.    Research is uncovering how to recognize similarities between content and then organize it into databases that can be manipulated intuitively by the average user to create new content that is derived from the existing content.  The following 3 papers all contribute to the establishment of this capability:   content creation, edit and compare 3D shapes .

One exciting new technology allows content creators to de-animate only part of a moving video for emphasizing certain life-time adventures or for emphasizing items of interest in advertisements,  etc.

Read on for individual paper topics and how their research will enhance virtual environments.

Optimizing Locomotion Controllers Using Biologically-Based Actuators and objectives

• First ever technique that do not rely on motion capture data to achieve virtual objects locomotion
• Demonstrates biologically-based actuators and objectives that matches real human-like gaits
• Technique automatically synthesizes walking and running controllers and operates without the use of motion capture data.

Continuous Character Control with Low-Dimensional Embeddings

• Humans learn a lot of movements upon observation because they are able to generalize the style and repurpose it for striking etc.
• Such generalization is a challenge for character animation as it requires users/programmers to “spell out” the desired behavior with a comprehensive set of motions and extensive programming.
• In this paper, the author presents a new technique that animates characters performing user-specified tasks by generalizing from a small number of example motion clips into a continuous space of stylistically consistent motions.

Schelling Points on 3D Surface Meshes

• This paper investigates focal points or “Schelling points” on 3D surfaces to develop a model of salience. The prediction of model of salience is the fundamental problem in applications such as shape matching and online games where winning of a game depends on selecting most salient points without any communication among the players.
• This paper publishes a unique technique that develops model of salience on 3D surface meshes based on social/psychological definition also known as “Common knowledge” about feature points on 3D surfaces.

Stitch Meshes for Modeling Knitted Clothing with Yarn-level Detail

• Knitted Cloth simulation with yarn level details has remained a challenge in computer animation industry. There is a lot of guess work involved in understanding the cloth movement that is based on different stitching styles.
• This paper describes a first modeling technique that can efficiently create yarn-level models of knitted clothing with a rich variety of patterns that would be completely impractical to model using traditional techniques.
• By leveraging the 6-step process described in the paper an artist can create a rich variety of knitting patterns with full scale garments for virtual characters.

Printing Spatially Varying Reflectance for Reproducing HDR Images

• HDR is used imaging and photography to allow greater dynamic range between the lightest and darkest areas of an image to represent more accurately the range of intensity levels found in real scenes.
• When traditional photographs are printed, the range of brightness can be heavily compressed, and the result can look flat. This paper presents a solution for viewing high-dynamic-range (HDR) images using a reflective sheet of paper, glossy ink, and a torch light illuminating the paper. With the proposed technique, one can get a better sense of the range of brightness in the scene and adjust it by moving the light or the paper.

HelpingHand: Example-based Stroke Stylization

• The appearance of strokes in digital drawing depends not only on the path of the stylus but also on 2D position, pressure, 2D tilt and rotation of the instrument.
• Digital artists often use a highly quality stylus coupled to a virtual brush to produce expressive strokes in their own style. However, such devices are difficult for novices to control and many people draw with less expensive input devices.
• This paper describes a method whereby a non-expert draws a 2D query stroke using an inexpensive input device, and missing hand gestures are synthesized based on a library of examples supplied by an artist. The resulting marks follow the trajectory drawn by the non-expert but convey the gestural style of the artist.

Manifold Exploration: A Markov Chain Monte Carlo technique for rendering scenes with difficult specular transport

• In traditional techniques it is difficult to render a scene that involves specular lights paths such as a tabletop seen through a drinking glass sitting on it. However, these glossy objects are being used everywhere in animation industry and has become an important material that needs realistic rendering in virtual scenes.
• This paper presents a Manifold exploration, a new way of handling specular paths in rendering. The technique is on sets of paths contributing to the image naturally form manifolds in path space, which can be explored locally by a simple equation-solving iteration

Bidirectional Lightcuts

• Computing the visually important effects in a modern interior that may include fabrics such as drapes, sofas, clothes, where volumetric representations represent yarns at micron resolution; polished metals in appliances like refrigerators and faucets; wood in furniture and floors; complex lighting fixtures; and building materials like granite and marble, is challenging and requires unified support for light transport with high gloss reflections, subsurface and simulation complex light sources.
• Today, designers choose existing ray tracing and light transport protocol that are within computational budget that result in noisy images even with high computational times.
• This paper presents novel strategies for handling light paths for efficient generation of low noise images.

A Probabilistic Model for Component-Based Shape Synthesis

• The creation of compelling three-dimensional content is a central problem in computer graphics. Many applications such as games and virtual worlds require large collections of three-dimensional shapes for populating environments, and modeling each shape individually.
• Tools for automatic synthesis of shapes from complex real-world domains must understand what characterizes the structure of shapes within such domains. Developing formal models of this structure is challenging, since shapes in many real-world domains exhibit complex relationships between their components.
• The focus of this paper is on designing a compact representation of these relationships that can be learned without supervision from a limited number of examples. The key idea in the design of the model is to relate probabilistic relationships between geometric and semantic properties of shape components to learned latent causes of structural variability, both at the level of individual component categories and at the level of the complete shape.

Synthesizing Open Worlds with Constraints Using Locally Annealed Reversible Jump MCMC
No pre-print yet

Exploring Collections of 3D Models Using Fuzzy Correspondences

        
• Large collections of 3D models are now commonly available via many public repositories, opening new possibilities for data mining, visualization, sorting, comparing and synthesis of new models. However, the task of exploring such 3D collections remains challenging. It is because today while most online databases make it easy for users to select sets of similar models using text-based filtering, understanding the similarities and differences within such collections is difficult because most 3D models are not in a consistent orientation.
• This paper presents a new analysis tool and exploration interface for 3D model collections. The tool allows users to directly specify regions of interest (ROI) on example shapes in order to guide subsequent exploration actions. The tool is robust and efficient over existing alternatives and is interactive exploration tool for large model collections that uses fuzzy correspondences to support view alignment, ROI-based similarity search, and faceted exploration.

Selectively De-Animating Video

• The large-scale motion of an object can sometimes make it difficult to see its finer-scale, internal motions, or those of nearby objects.
• In this paper, we present a semi-automated technique for selectively de-animating or removing the large-scale motions of one or more objects. The user draws a small set of strokes indicating the regions of the objects that should be immobilized and our algorithm warps the video to remove the gross motion of these regions while leaving finer-scale, relative motions intact.

Symmetry-Guided Texture Synthesis and Manipulation

• Many materials have textures (fine-scale, high-frequency variations) organized in distinctly recognizable spatial patterns (large-scale,low-frequency variations). For example, tiger pelts have fine-scale fur textures organized in large-scale striped patterns; floor carpets have fine-scale weave textures organized in large-scale ornamental patterns; and, brick walls have fine-scale mud textures organized in a large-scale block patterns. The key challenge in modeling these patterns is to provide a way for the user to guide the synthesis process, that is, specify what spatial patterns should appear in the output image.
• This paper presents an idea that representations in symmetry space are a natural way to describe spatial patterns in many real-world textures. We also provide a framework to investigate this idea which includes a variety of methods for symmetry representation, objective function specification, and image optimization. Different combinations of the methods are shown useful for symmetry transfer and symmetry processing.

Structure-aware Synthesis for Predictive Woven Fabric Appearance

• Woven Fabrics have a wide range of appearance determined by their small scale 3D structure. Building these yarn-level models using existing techniques is challenging due to the manually intensive process that often fail to capture the naturally rising irregularities which contribute significantly to the overall appearance of the cloth. Existing techniques also do not automatically adapt to the different fabric designs and only rely on scanned samples.
• To overcome the limitations described above the papers presents a novel approach of creating models of woven cloth which user specified fabric designs and produces models that correctly capture yarn level structural details of cloth.

An Algebraic Model for Parameterized Shape Editing  

• Today creating 3D environments is difficult due to the fact that it’s hard to create and easily adapt existing shapes to new shapes. Structure aware shape editing software tools that are available today can only allow the user to enable the user to edit high level shapes. It cannot alter the topology of the object.
• This paper presents a 3-step structure adaptive shape editing tools that lets users to edit topology while maintain global characteristics.

Simple Formulas For Quasiconformal Plane Deformations
No preprint available

Exposing Photo Manipulation with Inconsistent Reflections

• The advent of sophisticated photo editing software has made it increasingly easier to manipulate digital images. Often visual inspection cannot definitively distinguish the resulting forgeries from authentic photographs. In response, forensic techniques have emerged to detect geometric or statistical inconsistencies that result from specific forms of photo manipulation.
• This paper describes a new forensic technique that focuses on geometric inconsistencies that arise when fake reflections are inserted into a photograph or when a photograph containing reflections is manipulated.

Energy-based Self-Collision Culling for Arbitrary Mesh Deformations

• Self-collision detection (SCD) methods are widely used in computer graphics and engineering to enable realistic simulation of self-contact for highly deformable objects. Various methods have been devised to accelerate the numerous triangle-triangle overlap tests for realistic object movement simulation
• This paper describes a method that accelerates self-collision detection (SCD) for a deforming triangle mesh by exploiting the idea that a mesh cannot self-collide unless it deforms enough. Unlike prior work on subspace self-collision culling which is restricted to low-rank deformation subspaces, our energy-based approach supports arbitrary mesh deformations while still being fast.

Motion-Driven Concatenative Synthesis of Cloth Sounds.
No Preprint yet

Precomputed Acceleration Noise for Improved Rigid-Body Sound

• The rattling of coins dropped on a table, the jingling of a set of car keys and the cascade of noise from a shattering pane of glass are all familiar sound phenomena. Simulation of rigid-body dynamics for scenarios such as these is a widely studied field in the computer animation community.
• Rigid-body impacts produce sound primarily due to two sources: “ringing noise” and “acceleration noise”. Ringing noise refers to sound due to object vibrations. Acceleration noise, on the other hand, is produced when objects undergo large rigid-body accelerations. If a body experiences acceleration over a sufficiently short time scale, the resulting pressure disturbance in the surrounding medium is perceived as sound. While current rigid-body sound models synthesize convincing ringing noise, no efficient models exist for synthesizing sound due to acceleration noise. Consequently, synthesized rigid-body impact sounds tend to have an incorrect initial attack and lack the “crispness” characteristic of real impact sounds.
• To address this limitation, this paper proposes a simple and efficient model for acceleration noise which can be easily integrated with existing rigid-body sound pipelines for realistic experience.

Updated Sparse Cholesky Factors for Corotational Elastodynamics
TBD

Social Computing is the study of information technologies and digital media as social and cultural phenomena.  While this has always been the case since the beginnings of the computing industry, the rise of social networking systems, Web 2.0, cloud and embedded computing, and the proliferation of ways and places to access digital media, this value, indeed necessity, of this perspective is increasingly clear.  For example, the tremendous success of Facebook and Twitter can only be understood as much the result of social processes as technological ones.  This and many other cases point to the pervasive entanglement of the social and technical worlds, and a pressing need for new paradigms for the design and analysis of technologies, paradigms that are rooted in the theories and methods of the social sciences and humanities as much as they are in engineering and the hard sciences.

For too long, social scientists and technologists have worked as if their domains were essentially independent.  In certain special cases the two communities have come together, productively, to understand and build devices, products, and services that could not be realized without such collaboration.  In the 70s and 80s, as time-sharing and PCs brought computing power to mass audiences, we saw the rise of human-computer interaction, and new or newly prominent professions like “human factors engineer” and “interaction designer”.  Likewise in the 90s and 00s, the rise of the consumer-based internet economy required and built upon different kinds of dialogs between technologists and people-focused disciplines like “ethnographic consumer research” and “experience design”.

Technology is now instrumental in defining who we are, how we think about ourselves and our lives, and how we act individually and collectively.  With sensors, clouds, and pervasive possibilities of access, we no longer have to actually use technology to be affected by it.  Can you really remain unaffected by Facebook even if you opt out of it, if your friends, relatives, and future employers increasingly rely on it?  As a culture can we afford to accept as given the trending topics algorithm on Twitter or the search algorithms of Google, if these substantially shape what gets noticed and what gets bypassed by our attention and interests, individually and collectively.

The time is ripe, for Intel and for our industry, for new ways of thinking about, managing, and creating technology.  The technology-infused worlds we live in, and our children will live in, demand different, more productive conversations between engineers, architects, producers, and regulators of the technologies that will underlie tomorrow’s organizations, societies, and cultures, on one hand; and the anthropologists, cultural theorists, science and technology studies scholars, and critical design researchers who are centrally concerned with the nature, origins, and futures of these organizations, societies, and cultures, on the other.

The mission of the Social Computing center is to help create these new dialogs and collaborations.  It is organized around five research themes:

• • Materialities of Information:  re-thinking “information” as grounded in materials and physical objects.
• • Subjectivities of Information:  moving beyond “the user” as the center of user-experience and user-centered design.
• • Information Ecosystems:  How we relate to each other in, around, and through data.
• • Creativity and Collectivity:  Group-embedded technical creativity and how it can change the world.
• • Algorithmic Living:  Digital representations and algorithms that change how we understand ourselves.

Research activities will span across one or more of these themes.  For example, as part of a project looking at food security and cyberinfrastructure, center researchers will be conducting a case study of Benefits CalWin, an e-government initiative of the State of California to provide services to the state’s food-insecure populations.  By evaluating the design of the online application portal, ethnographically engaging with the practices of outreach workers, and designing and building technologies to support these workers in helping their clients, this project will contribute to the Materiality, Ecosystems, and Creativity and Collectivity themes.  And beyond the question of food and responsibilities of states, it may also produce insights applicable to Intel’s efforts to reach out and provide service to different stakeholder communities.

We look forward to engaging with stakeholders across Intel who are planning for and building tomorrow’s products, services, and infrastructures.  For more information, please contact us or consult our website, socialcomputing.uci.edu.

I was asked to speak about the importance of U.S. innovation to job creation, the economy and the future of U.S. competitiveness, so I took the opportunity to discuss how Intel undertook a transformation in our approach to research and innovation and how far we’ve come in the past few years. We view this approach as a 21^st century model of industrial research in contrast to the 20^th century model of Bell Labs and the many U.S., European, and Asian companies that copied the Bell Labs model.

I’ve received several requests for the text from the speech, so I’ve included it below.  Enjoy.

The U.S. Innovation Summit 

The Newseum, Washington, D.C.June 20, 2012 

Prepared Speech by Justin Rattner, Intel CTO

Thank you and good morning.

It’s a pleasure to be here today to discuss the importance of innovation to the economic future of the United States.  I’ll try to avoid the usual platitudes and get right to what I think U.S. industry needs to do to get its innovation house in order.

It is no doubt clear to those of you who work inside the beltway that the word “innovation” is on the lips of everyone from corporate executives, government leaders and university presidents.  Each of them talks about the need for the U.S. to accelerate its pace of innovation or be overrun by innovation coming from virtually every other point on the planet. The message is simply: innovate or die.

Unfortunately, many of these same leaders often confuse innovation with ideation and that in my judgment is a critical, if not fatal, mistake. As the CTO of a major technology company, I am constantly exposed to new ideas for all manner of products and services. They’re ideas bubbling up in my organization and ideas streaming in from our customers and our collaborators, from both industries and universities. Ask any VC if he or she is lacking for ideas. They’ll tell you the same thing. Ideas are cheap; a dime a dozen. Innovation, not ideation, is where we need to focus.

Another common confusion is over the difference between invention and innovation. Every time I hear people reminiscing about the good ol’ days of research when Bell Labs or IBM Research was winning another Nobel Prize or Xerox PARC was off inventing the future of computing, I just cringe. While those industrial-scale research labs of the 20^th century were great inventors of things, from the first laser to the laser printer, they were absolute disasters at making them practical and getting them to market. Despite the fact that most of these labs were part of very successful manufacturing companies, the labs themselves had little interest or desire to move their ideas to market. This must be considered their fatal flaw.

Another common belief is that most new ideas are brought to market by entrepreneurs funded by venture capitalists. While venture capital is a great U.S. success story, and Intel Capital is one of the largest venture capital groups in the world, venture-funded businesses represent a relatively small portion of the innovation taking place across U.S. industry. Most innovation is, in fact, done by mid to large sized companies who must continually innovate to stay in business. This is especially true in the information and communication technologies where much of our economic future will be won or lost. The question we must answer and answer quickly is how do we turbo-charge industrial innovation in the 21^st century to ensure U.S. economic and, therefore, global leadership for decades to come.

I believe that transforming the way the U.S. does industrial research is the key. I want to spend the rest of my time talking about how we undertook such a transformation at Intel and how far we’ve come. We think of it as a 21^st century model of industrial research in contrast to the 20^th century model of Bell Labs and the many U.S., European, and Asian companies that copied the Bell Labs model.

It may surprise you to hear that for the first two decades of its existence, Intel consciously avoided using the term “research” to describe anything that was not strictly product or technology development. The origin of this “no research” thinking dates back to the time when Intel’s founders, Robert Noyce and Gordon Moore, were running Fairchild Semiconductor in California. Despite invention after invention, from the planar transistor to the silicon-gate MOs technology, Fairchild struggled to move new semiconductor technology out of its research lab and into Fairchild’s products.

When Noyce and Moore left Fairchild to found Intel in 1968, they agreed that there would be no line dividing semiconductor research from manufacturing at Intel. New devices and processes would be developed on the factory floor alongside the processes then in production. It wasn’t until the mid-80s before a small research team was allowed to form. Called Components Research, it has become the principal engine for semiconductor technology innovation at Intel.

Many of the stunning Intel chip innovations you’ve read about in the last half-dozen years were invented by this one, fairly small, research team, but what separates them from others in our industry is how they get these inventions out of the lab and ready for manufacture. The key is a process we call pathfinding, and I’ll talk more about the critical role it plays at Intel in just a few moments.

Before I do that, let me take you back to late 2006, when Intel launched a broad restructuring program intended to support a new business model for the company. Virtually every part of Intel was analyzed and restructured to match the new model. No part of the company was safe and that included research and development. One aspect of R&D that received considerable attention was the interface between the primary research arm of the company, Intel Labs, and its primary product development arm known as the Intel Architecture Group or simply IAG. Of particular importance was the question: how do we dramatically improve the transfer efficiency or “hit rate” of new technologies coming out of Intel Labs and going into IAG’s mainstream products.

The analysis clearly showed that our low hit rate was not a reflection of the relevance or importance of the technology coming out of the Labs, but was due in large part to timing differences between the completion of the research work and the start of product development. Too often a research project would be complete, but there were no developers ready to pounce on the results and get them ready for product development, a phase we call technical readiness.

After months of unsuccessfully shopping a new technology, a research team would move on to their next project and the motivation to transfer their earlier work would fade. Similarly, when a development team would come by looking for new ideas for their next product, the research team had little interest in returning to what they viewed as yesterday’s news. We came to refer to this synchronization problem as “the valley of death” given its remarkable ability to kill perfectly good technologies before their time.

The solution to the problem, as it turned out, was right under our noses. Of particular interest was the way our semiconductor manufacturing R and D teams bring the next generation semiconductor technology to market. The key being a process they call, you guessed it, pathfinding. Interestingly, there is no pathfinding department at Intel. In fact, only one scientist and one admin are permanently assigned to pathfinding. In place of a standing army of pathfinders, a pathfinding team is assembled for each generation of chip technology. The team is made up, and this is the secret, of both researchers and developers for a sufficient period of time, typically 12-18 months, to bring about one or more successful technology transfers. With a 100% success record of the last two decades, we knew we were staring the solution in the face. The challenge Intel Labs and IAG set out to solve was how to scale out the pathfinding process to cover the literally dozens of new technologies that go into a new Intel chip or system design.

Despite our fears, adapting the pathfinding process to these numerous areas of research has been a remarkable success.  Just to give you one example, you may have heard of McAfee’s DeepSAFE anti-malware technology, the first commercial defense against zero-day, rootkit, cyber-attacks. In plain English, that means defending against Stuxnet and Aurora. What you may not know, is this technology was invented by Intel Labs and then jointly developed for the market as part of a 3-way pathfinding effort between Intel Labs, Intel IAG, and McAfee over the last two years. Now that McAfee is an Intel company, there are many more pathfinding projects underway between Intel Labs and McAfee. Look for these coming to market over the next three years.

Our pathfinding process has become so successful that today the Intel product groups literally fight over the pathfinding slots. It’s also not unusual for more developers to be assigned to a pathfinding project than researchers. At any moment, we have over 50 distinct joint pathfinding projects between Intel Labs and the various product development teams.

While roadmap impact is certainly a critical part of being a 21st century industrial research lab, it is not the whole story. To better understand what works and what doesn’t work in modern industrial research and how it differs from academic research or government research, we initiated a benchmarking effort with various multi-national, industrial research labs around the world. Included in the study were many well-known industrial labs including IBM Research, Microsoft Research, Google Research, and GE Global Research. We looked at about a dozen different labs in all.

Among the things we learned from the benchmarking effort was the importance of balancing research directed at existing product lines and research aimed at exploring technologies that have no immediate business impact or even relevance. For the last four years we have spent half of every dollar on business-directed research and the other half on what we call exploratory research. This 50-50 balance has worked remarkably well. While it would be easy to argue for a much higher spend on the business-directed side, we feel we create much more long-term value for Intel by keeping exploratory research and business-directed research in equal proportion.

We also recognized that not all the smart people in the world work for Intel. Collaboration is a powerful tool to expand on and amplify research results.  Such was the case with Apple with whom we worked to create the Thunderbolt I/O technology now found on every Macintosh.

Collaboration turns out to be especially important when working with the university community. To that end, Intel has built its own worldwide university collaborative research network including what will soon be seven Intel Science and Technology Centers (ISTCs) in the U.S. and five Intel Collaborative Research Institutes (ICRIs) in Europe and Asia. We look to these centers and institutes for the long-range research work that was typical of that being done at Bell Labs in the 40s and 50s and Xerox PARC in the 70s and 80s. Each center or institute is led by a “hub” school and spans multiple “spoke” universities, designed to form a new, multidisciplinary community of the best researchers from around the world in a given field.  Critically, we locate senior Intel researchers at the affiliated academic institutions, where they can work side-by-side the top researchers in the U.S. and the rest of the world. The Intel researchers report directly to the various research groups at Intel Labs and are the principal means, along with hiring the best students, for bringing the academic breakthroughs to Intel.

At this point you may be thinking that 21^st century industrial research is all about creating the great technologies that enable the great new products and services to come to market. Let me suggest that it is just as important for the research organization to prevent poor technologies from ever reaching the market. As you can imagine, product failures in the chip business are extremely expensive. A typical mainstream microprocessor may cost upwards of $600 million dollars to develop. More significantly it will be built in a factory that costs ten times as much to construct. If the product flops because of a bad technology decision, it’s a really big problem. Yet, such failures can and do happen, and more often than you might suspect.

What a 21^st century research lab can do is vet those new ideas, validate the good ones and weed out the bad ones. This is called “failing fast” and it’s something we consider to be as important to the success of Intel as anything we do on the innovation side. We believe it should be the responsibility of every industrial lab of a certain scale to celebrate this kind of internal failure as much as it celebrates its external successes.

While Bell Labs may have been the model of 20th century industrial research, and there are still a number of companies chasing that vision, it is increasingly dated and out of step with today’s fast moving information and communications technologies. We are trying to set a new course for 21^st century industrial research and hope many other companies will join us in this important transformation and not simply for their own near-term success, but for the long-term success of the nation.

Thank you!

Sorting is a core concept in computer science and is a fundamental building block for efficient data structures and algorithms. As a result, some form of sorting is used in almost all applications, and is crucial to many important services, including database and web queries. Results of a query are generally sorted and presented to the user in some useful order, e.g., by relevance, by cost, chronological, etc. Under the covers, many systems also internally sort and index data for fast retrieval and updates. In some applications, improved sorting allows faster responses, or better responses that take more data into account. More generally, improving the performance and efficiency of such core algorithms helps improve the infrastructure of the Internet, reducing costs of deploying web services, improving densities and operating costs of data centers, and allowing the entire system to scale up to more services and users.

Although the theory and algorithms for sorting have been studied for decades, sorting is still of significant interest today because sorting large datasets stresses almost all of the major components in a computer system. These include both hardware and software components, such as the processor, memory, busses, operating system, file system, and disks. The goal of the Joulesort competition is to build a system that can sort a large dataset with the least energy consumed.

Our team, consisting of Intel Labs researchers Michael Kaminsky, Michael Kozuch, and myself, along with Carnegie Mellon University professor Dave Andersen, built the record-setting machine around an Intel® Core™ i7 2700K, a high-end 2nd Generation Core desktop processor. Rather than limit ourselves to low-power systems, our strategy focused on a moderate-power, balanced system that gets the job done fast enough to justify the higher power draw. Since the total energy consumed is the product of power (Watts) and time, by reducing the total execution time by a larger percentage than the increase in power, we were able to achieve a reduction in energy consumption compared to low-power systems.

To keep the i7 processor fed and running flat out, we coupled it to two Intel RAID cards and attached 16 Intel 710-series SSDs. These provided 4.8 TB of fast flash storage. At peak, the system was able to read and process data at 3.8 GB/s (approximately a DVD’s worth of data every 1.25 seconds!). Yet, the average power stayed below 170W. The combination of modest power and high performance made this a record-breaking system in three size categories, beating the existing records for energy-efficient performance in the 10GB, 100GB, and 1TB Joulesort benchmarks by 2.6%, 33%, and 729%, respectively.

With the slate of exciting recent product releases, including 3rd Generation Core microprocessors, dual-socket Xeon® servers, and fast SSDs (520 series, and 910 series PCIe-attached devices), our team hopes to continue to create record setting systems that push the state-of-the-art in energy-efficient computing.

We opened this center to address the unprecedented growth in digital data and the issues that it entails. In the future, this is likely to accelerate even further through more pervasive use of digital media, ubiquitous connectivity, growing use of smart mobile devices, growing penetration of geo-spatial mapping and round-the-clock sensing. This data flood will be large in size, multi-dimensional and highly correlated. Storing and providing unique visualization techniques to efficiently parse and extract meaningful information from this data is key, and it is the ultimate goal of the center.

With this in mind, this new ISTC for Big Data will explore data analytics to support data-intensive discovery including database management, analytics and visualization support for massive datasets and their implications for computer architectures.

Expanding on this, the research at this center will focus on exploring the challenges and opportunities associated with Big Data including

A) Designing and prototyping hardware and software for storing, managing, processing, understanding, and visualizing “big data”. This includes user interfaces and data visualization.

B) Discovering novel algorithms and scalable, co-designed architectural alternatives for effectively dealing with the three inherent attributes of big data: massive, unstructured, and dynamic;

C) Innovative ways of exploiting modern processor technology trends such as, multicore, manycore, and emerging non-volatile memory technologies

The research could have impact in several areas. Financial services applications are an example of business with big data challenges, as they look for patterns to try to make sense of the huge streams of data.

In science, there’s already a huge volume of data that needs to be processed in areas like astronomy (to make sense of Petabytes of data from telescopes) or genetics (with experiments on gene expression with the hope of creating more customized treatments for people), as well as medical collaboration and diagnosis.

Another area is “urban-scale sensing” where cities have the potential to generate massive amounts of data from GPS-enabled vehicles and other devices, electricity and water monitors, and weather and air quality systems. The research would help with storing the data and making sense of it so that the city managers and inhabitants can benefit.

We expect synergy between this new center and the other ISTC centers, such as the ISTC for Cloud Computing and ISTC for Embedded Computing.

The leaders of the center are Dr. Sam Madden (Academic PI) and Dr. Michael Stonebreaker (Academic Co-PI) both at MIT, Dr. Pradeep Dubey (Intel PI), and Dr. Jeff Parkhurst (Intel program director).

Education Day & Setup

Maker Faire started off with a bang with Education Day, two days before the main faire opened. Nearly 2000 students toured a selection of booths and exhibits to get a taste of what Maker Faire is all about. Around 90 volunteers from Intel, most from the Interaction and Experience Research Group at Intel Labs, acted as tour docents to help the student groups navigate the space.

Featured on the tour were a group of Intel Makers: Intel Labs employees who participate in the Maker movement in their spare time. Mario Alzate showed off his homemade electric-power tricycle and Eric Salskov found it easy to demonstrate his wind turbine in the gusts that blew across the San Mateo site. Lucas Ainsworth displayed his mechanical cardboard Kinetic Creatures while Jay Silver encouraged kids to make music with bananas and a Makey Makey kit.

Intel family members got involved too, with Karen and Josh Tanenbaum showing off their Steampunk props and superhero, Captain Chronomek and father-son duo Jim and Schuyler St. Leger printing Intel keyfobs on a MakerBot. Vicki Fang’s Peacock Chair was put out of commission by an early morning power surge, but still made a lovely display, and Mikal Hart showed off his Arduino-based “reverse geocaching” puzzle box, which demands to be taken to a specific location before revealing its treasures. Pete Denman demonstrated his custom wheelchair, electronics, computer interfaces, and utensils as well as provided kids an opportunity to create a collaborative art piece.

At the end of Friday setup, as the Makers put the finishing touches on their exhibits before opening to the public Saturday morning, Intel sponsored the traditional paella dinner that serves as a kickoff for the Faire.

Make Your World Booth

Intel Labs and the Lab at Rockwell Group co-sponsored the Make Your World booth, a playful environment for kids to learn about basic circuits and interactivity.

The walls of the booth held an assortment of Arduinos, lights, motors, and audio outputs, accessed via small gold terminals sticking out of the wood. Visitors to the booth were given alligator-clip wires that allowed them to complete the circuits by connecting terminals and seeing the effect in the space: blinking lights, spinning objects, funny sounds, and more.

Kids who wanted to learn more were encouraged to take part in our switch workshops, where they used foam board and tin foil to create more complex inputs to control the circuit. We also gave away sticker sheets of different “inputs” and “outputs” and a take-home kit containing supplies for making a simple circuit out of copper tape, LEDs and a battery. Many of the stickers ended up on the booth itself, along with notes, doodles, and other decorations.

Computer Controlled Orchestra

The Intelligent Systems Group, in collaboration with Sisu Devices, showed off the Computer Controlled Orchestra throughout the Faire in the Fiesta Hall. Intel Atom processors power a complex mechanical system that uses paintballs to play musical notes in a highly coordinated and graceful ballet of sound and motion.

Video of Intel’s Computer Controlled Orchestra

Maker Education Initiative

Perhaps most significantly, Maker Faire 2012 witnessed the founding of a new non-profit organization, the Maker Education Initiative (MEI), of which Intel (through our Corporate Affairs Group and the efforts of Carlos Contreras) is a cornerstone partner.  Along with Intel, the Maker Education Initiative’s founding sponsors are Cognizant and O’Reilly Media, and the goal of the organization is “to create more opportunities for young people to make, and, by making, build confidence, foster creativity, and spark interest in science, technology, engineering, math, the arts—and learning as a whole”. The MEI announcement got re-blogged and tweeted by the White House Office of Science and Technology Policy.

Why focus on cities? More than 50% of the world’s population live in cities. Moreover cities consume more than 75% of the world’s energy as well as contributing approximately 70% of greenhouse gases. By 2050 over 70% of the world population shall live in Cities. Cities are places where people meet, exchange and interact. They bring people with different interests, experiences and knowledge close together. They are the centres of culture, economic development and social change.

At this London-based institute; Intel principal investigators (PI’s) shall collaborate with PI’s from  Imperial College London and University College London to drive new frontiers in the application of computing technologies to advance the social, economic and environmental well being of cities. Together we envisage the opportunity to collectively research and create the evolutionary leap for cities in terms of resource efficiency, new services and ease of living. Using a quadruple helix innovation approach involving Government, Industry, Academia and city dwellers we hope to catalyze and drive a new vision for sustainable cities.

Why London? London is the 5th largest city in the world, it has the largest GDP in Europe, and with over 300 languages and 200 ethnic communities, its diversity is a microcosm of the planet itself offering an exciting test bed to create and define sustainable cities. London is the host city to the 2012 summer Olympic games, and we shall seek to understand the experiences of a city under pre-planned stress. What systems worked, failed and why? How were the daily lives of the denizens, workers, and businesses of London affected?

 What shall we do?

- We aim to create new, cross cutting inter-disciplinary “Systems of Systems” Cities research  methodology to understand key city challenges and technology opportunities.

-We shall create a citizen-lead, technology enabled research agenda

- We shall create cross sector urban infrastructure solutions & services

- We shall partner with London communities and authorities to validate / test our research hypothesis.

- We shall collaborate with fellow travellers to envision future sustainable cities.

Sample research topics:

Citizens and Community :

• How can technology “sustain sustainable behaviours”?
• How can you design and evaluate connected and sustainable services and user-centred information for diverse needs of city dwellers.
•  How do you engage city communities to participate in developing technological innovations that will improve their environment, transport systems and local services

City as a Platform

• What are the system architectures that would compose the notion of the city as a platform?
• How can edge nodes compose an adaptive, resilient urban membrane?

Big Sensor Data Management and Analytics

• How do we architect distributed analysis, decision making and resilience from dust to edge to cloud?

Human,  Environment Interface

• What novel interfaces and interactions are required to encourage participation of citizens, business and government?

Privacy, Security & Trust

• How do we protect privacy, security and disconnection in a city of a billion sensors?

Integrated Urban Services

• How can technology enable ubiquitous integrated services?

Policy + Business Models

• Who pays? Who repairs? Who profits?

The institute will engage with local communities to understand how they want to live in their cities and involve them in designing technological innovations. These innovations will include making cities more ‘aware and adaptive’ by harnessing data gathered through sensor technologies embedded in city infrastructure and data shared by communities.  The institute will use this data to develop models for more sustainable behaviour, including community energy management or water conservation. The institute will also explore how fixed and mobile sensors across the city including intelligent connected vehicles, can be used in the collection of data on the weather,  emissions and traffic flows, for use by city planners in the development of more sustainable cities in the future.

We passionately feel the institute shall contribute to Intel’s Vision:-  “This decade we will create and extend computing technology to connect and enrich the lives of every person on earth “

Within the Intel Collaborative Research Institute for Sustainable Connected Cities – London; the team are highly excited to collaborate and vision future sustainable cities.

Author:

Charlie Sheridan – ICRI Sustainable connected cities PI & managing sponsor

Contributors,

David Prendergast – ICRI Sustainable connected cities, Intel social science (PI)

Martin Curley – ILE Director

Prof. Yvonne Rogers, University College London (PI),

Prof. Julie Mc Cann, Imperial College London (PI)

The institute will be based in Israel at the Technion in Haifa and the Hebrew University in Jerusalem (HUJI). The Institute is co-led by Ronny Ronen (Intel, Senior PE), by Prof. Uri Weiser (Technion), and by Prof. Naftaly Tishby (HUJI). It will also draw researchers from other Israeli universities.

Bringing together a multi-university team that includes the top minds in the field of machine learning and computer architecture, Intel wants to accelerate the fundamental research in 3 major themes:

• Advanced Machine Learning. Future devices will use a lot of data arriving from various sources (sensors, web etc) at high rate. Making fast, real time, intelligent decisions requires new type of machine learning algorithms;
• Brain-inspired computing. Humans easily outperform computers in many domains, especially in learning and recognition tasks. We will apply the deep understanding of brain fundamental structures, principles and mechanisms to explore new, computing architecture that can do these tasks better than traditional computers.
• Novel heterogeneous computing platforms, accelerators. Future usages demand a lot of computing power at tight energy budget to perform tasks like speech and gesture recognition. A promising way of bringing such performance demanding tasks to low power mobile devices is through heterogeneous systems, where several building blocks, differing in their capabilities and performance/power characteristics, are combined. The Institute will also investigate the applications of novel machine learning methods in traditional processor architecture to achieve higher performance and efficiency at reasonable complexity.

The institute will apply findings of the above fundamental themes into two applications areas and examples of usage scenarios:

• Intelligent Agents. We envision future devices which use machine learning to proactively assist the user’s daily activities, based on data coming from “real” sensors as well personal and global data accumulated over a long time via many sources.

Imagine that you just landed in a city you have never visited before. It is quite late and you do not speak the local language. The intelligent device – or agent – will direct you to the taxi station nearby. When you are at the hotel it will suggest a good Italian restaurant in the neighborhood, knowing you like Italian cuisine. It will also remind you to take a coat since it is cold out there…

• Learning Audio/Visual Systems. Most of the world’s data today consists of video and audio streams. The amount of data exceeds the human ability to view and infer from. We envision systems that use machine learning to automatically analyze this data and extract useful relevant information.

Recent series of criminal incidents impacts people’s sense of security. Future security cameras will not only record the activity nearby, but will be able to identify exceptional events w/o human intervention and initiate timely actions to prevent them and identify the criminals.

As in other Intel Science and Technology Centers funded by Intel, the Collaborative Research Institute for Computational Intelligence will be based on truly open IP model to foster an innovative ecosystem that will lay a foundation for future computing paradigms and usages.

While the benefits to society are enormously valuable, this trend also introduces substantial security risks. Mobile phones today store/process security-critical and privacy-sensitive data and will soon manage all aspects of an individual’s digital life. Similarly, tiny embedded controllers will control automobiles, homes, industry, and most other parts of our physical lives. To continue reaping productivity gains, we must mitigate these risks by dramatically increasing the trustworthiness of devices that form the bedrock of this connected world.

Today, we have launched the Intel Collaborative Research Institute for Secure Computing (ICRI-SC) @ TU-Darmstadt to address this urgent need. TU-Darmstadt is a top university in Germany and a major player in the EU for security research. The Center for Advanced Security Research Darmstadt (CASED) is the entity within TU-Darmstadt where security research is concentrated. The Institute will bring together thought leaders from Intel and CASED to conduct research and deliver early prototypes that demonstrate how to advance the trustworthiness (safety, dependability, reliability) of our mobile and embedded systems.

The Institute will focus on 3 research themes in the context of Mobile & Embedded systems:

• Novel Usage Models will be systematically explored in order to investigate the threat landscape and develop security architectures and requirements that deliver enhanced trustworthiness across a range of market segments. The initial focus will be on the automotive sector, exploring Car-to-Device applications that integrate mobile devices such as smartphones with in-vehicle systems in order to deliver converged solutions that enable improvements in driver and occupant comfort and safety.
• Secure System Software will focus on increasing the resilience of systems to today’s sophisticated malware. The emphasis will be on behavioural approaches such as control-flow integrity enforcement which will have an important role in moving beyond traditional signature-based anti-malware defences.
• Hardware Security Primitives will be investigated which enable security solutions to be extended to resource-constrained mobile/embedded devices, with focus on lightweight crypto building blocks, privacy preserving protocols and cost-effective HW trust anchors.

Only an integrated end-to-end approach, which is cognizant of the technologies from the resource-constrained embedded controller right up to the cloud-based server, is capable of delivering the safer mobile and embedded world we depend on. This is an ambitious as well as exciting research agenda. I eagerly look forward to the ICRI-SC making a significant and lasting impact towards “safer mobile & embedded computing”.

Intel has a major presence at the 2012 Maker Faire Bay Area as a Goldsmith sponsor of the event.  Intel was built by makers who envisioned a world of possibilities and instilled in our culture a deep rooted connection to tinkering and innovation.  Maker Faire is an opportunity for Intel and our community of makers to engage and share with other innovators who share these values.

In the West Lot, Intel Labs is running a large booth, cobranded and designed with The Lab at Rockwell Group (an architectural and environmental experience design agency in New York).  The theme of the booth is “Make Your World” and it encourages kids to start thinking about interactivity in their everyday environments.  The booth will have a series of building and making activities throughout the Faire weekend, plus periodic hands-on workshops, giveaways, and interactive displays.  Our goal is to inspire kids to think critically and creativity about the role of technology and interactivity in their lives, and to start to give them the tools to engage with and change their world.

The Corporate Affairs Group at Intel is also sponsoring Education Day, an event held 2 days before the main Faire where groups of students tour the Faire grounds and visit a selection of booths that are being readied for the weekend.  More than 80 Intel Labs employees, from the Interaction & Experience Research group (IXR) and other groups from across the company, are acting as docents to lead the estimated 2000 students on their tours as part of the Intel Involved volunteer program. Intel invests more than a $100 million a year in science, technology, engineering and math (STEM) programs because a solid math and science foundation coupled with skills such as critical thinking, collaboration and problem solving are crucial for their success.  Sponsoring events like Education Day helps encourage the next generation of young Makers and innovators who, Intel believes, are the key to solving our current and future global challenges.

Also at Education Day, there will be a special Intel booth featuring Intel employees who participate in the Maker movement.  They will demo and talk about some of the projects they’ve made in and out of the workplace, including electric vehicles, 3D printing projects, wearable electronics, and more.

In the Fiesta Hall, the Computer Controlled Orchestra will be demonstrated throughout the Faire.  Created by the Intelligent Systems group, Intel Atom™ processors and an array of sensors, lights, and motors create an intricate machine that uses airborne rubber paint balls to play beautiful music.

And finally, just before the Faire starts, Intel is sponsoring the traditional paella dinner for all the Makers on Friday night.  This event serves as the unofficial kick-off for the Faire, inaugurating a weekend of interesting talks, interactive demos, and amazing experiences.

Tickets are still available online or at the gate the days of the Faire, which runs May 19-20^th.   Hope to see you there!

Today’s TVs have numerous connectors to get video and audio into the device. Many TVs (however not many monitors yet) also have an Ethernet port to enable browsing or stream videos from online media streaming providers. From a purely technical point of view without the copyright issues, using IP connectivity to transfer data could just be the only input/output method we need. Considering the bit rates that current HD videos uses this could also be done over WiFi easily. For instance, Intel’s WiDi already demonstrates in the 1 device : 1 display setup to stream HD content wirelessly. As for handling the received, compressed video stream it is important to note that many SmartTVs already have the ability to efficiently decompress such data.

Variety of connecters on the back of a TV

Going back to the numerous connectors scenario there is another limitation we have lived with and got used to. Today we are mostly limited to 1:1 connections. One laptop connects with one cable to one TV. A second output source can be added by one more cable. Some graphics cards support multiple monitors at the same time but each monitor must be connected by a separate cable to the video card in the computing device. As the number of displays increases beyond what’s supported today by popular video cards, connecting these display devices becomes tricky. There is only complicated special solutions to deal with that the problem.

As the displays and the way consumers interact with their computing devices evolve, new scenarios arise. Think about using TVs, monitors and tablets together as output device?

The easy solution to all the above mentioned scenarios is the “Display as a Service” project (under the lead of Alexander Löffler and Jochen Miroll at the IVCI). There is the concept of a networked, virtual frame buffer (NetVFB). The NetVFB is used to coordinate between the image generators and all the displays. An application draws into that virtual frame buffer and the user specifies on his machine where and how (e.g. what size, rotated etc) it should be shown on the available displays.

1:n setup: App renders into virtual frame buffer. Using the network to transfer the image data to output on n displays.

“Display as a Service” has also been extended from the 1:n setup (1 driving machine, n displays) to an m:n setting – having more machines calculating an image and getting it merged together at the output displays.

m:n setup: Multiple apps or machines render into the virtual frame buffer. Output on n displays.

Of course synchronization becomes a very important topic when dealing with numerous displays. Researchers at the IVCI solved this by having a master screen that automatically synchronizes itself with the other displays over network. It works so perfectly that it can also be used with active stereo screens. And exactly such a stereoscopic display wall is what we would be happy to present you at CeBIT 2012, hall 26, booth F34.

* “Intel Visual Computing Institute” is a collaborative research institute at Saarland University, co-funded by Intel

With HTML5 and WebGL there is an opportunity to enrich the web with 3D content. However, for a regular web designer it is rather hard to get interactive 3D models integrated into their webpage and have them viewable across the compute continuum (from high-end workstation machines to mobile phones) due to the coding complexity and inability of the same code to work across different compute devices. This is where XML3D will likely play an important role in the future. It is an extension of HTML5 developed by the Intel Visual Computing Institute*, DFKI and the Saarland University under the lead of Kristian Sons.

XML3D enables a web developer to easily integrate 3D content into the web browser and to be able to use existing programming languages like JavaScript to interact with them. If for example a web designer would want to display a triangle, he would just add code like this:

(header)

<xml3d:int name=”index”>0 1 2</xml3d:int>

<xml3d:float3 name=”position”>0.0 0.0 0.0   1.0 0.0 0.0    0.0 1.0 0.0</xml3d:float3>

(footer)

Of course the full language offers much more like translating, rotating, scaling, materials, grouping, camera changes, dynamic manipulations etc.

One interesting aspect of XML3D is that is never forces a certain rendering algorithm. Therefore on a high-end workstation a higher quality, ray traced image could be calculated. Other devices could use WebGL or a completely different renderer for displaying the content.

The way to enable XML3D to the masses is not by a browser plug-in, but by defining it as a standard in the World Wide Web Consortiums (W3C) and to have it natively supported in the browser. A modified Firefox and Google Chromium version can be downloaded from XML3D website and experimented with. Let us know what you think. What are your thoughts on 3D in the browser? Where would you desire it the most? What new possibilities might arise with this? Tell us your opinion in our comment section.

Also we would be happy to welcome you at our booth at CeBIT 2012 in Hall 26, booth F34 and show you a live demo of XML3D.

* “Intel Visual Computing Institute” is a collaborative research institute at Saarland University co-funded by Intel

The first project under the collaboration is focused on the future of memory technologiesused in computing devices such as ultrabooks, laptops, tablets, and handhelds. By creating memories with much greater energy efficiency, these mobile devices will be better equipped to handle the data-intensive applications of the future. 

Our earlier collaborative work on memoryfor HPC has been very productive, so we were interested in a collaboration to explore further innovations in interconnect and memory architecture with a particular focus on mobile computing devices. 

Given that focus, our newly designated Taiwan Scientist in Residence, Dr. Wen-Hann Wang, suggested ITRI as a potential partner with close ties to industry and a proven record of making an impact with their research. For example, they helped to establish the semiconductor foundry industry with spin-outs such as TSMC. Their charter is a good match to Intel Labs, and they enjoy excellent relations with a broad cross section of the Taiwan IT industry that includes memory design houses, foundries as well as leading computing device OEMs & ODMs. Through ITRI, we may involve many of these industry players over time. 

Through Wen-Hann we connected with Dr. Cheng-Wen Wu, VP of ITRI and General Director of Information and Communications Research Labs, to set up the project which is starting under the very capable direction of our Dr. Shih-Lien Lu. 

I’m looking forward to an exciting and productive collaboration.

In computer science, “graphs” are a way to represent and explore the connections between things, such as all the stops in a subway system (pictured here for New York), all the links in a large computer network, or all the relationships between people on social networks like FaceBook. Graph computing is also used to discover meaningful correlations between events for applications such as medical informatics and cybersecurity.

However, these graph searches are challenging to compute efficiently because unlike a typical database, graphs vary wildly in size, shape and number of connections between nodes. The most interesting graph problems explore connections across large populations or massive datasets – billions of nodes with many more possible relationships between them. Drawing meaning from such “Big Data,” which could represent any type of business, scientific, or social information, is a key challenge for supercomputing and cloud computing alike. Since any node could lead to any other node (or nodes) in a vast web, it is difficult to predict which piece of data will be needed next, resulting in many trips to slower memory such as hard drives before then next computation can be performed.

Intel Architecture is well suited to graph problems because it has a cache hierarchy that is friendly to such irregular data access patterns. The challenge lies in creating the algorithms which effectively utilize this hardware.

Satish Nadathur, Jatin Chhugani, and Changkyu Kim of our Parallel Computing Lab were able to demonstrate the excellent processing power and energy efficiency of IA for the Graph500 benchmark. They achieved this result through innovative algorithm-architecture co-design which allowed the task to make much more efficient use of memory and compute on a Xeon (Westmere) cluster. Sandia Lab’s Richard Murphy, the owner of the benchmark, commended the team on an “outstanding job.”

Even more impressive than the raw performance was the efficiency of PCL’s algorithmic approach. Compare Intel Labs’ result with the #1 entry on the list from NNSA and IBM Research running on BlueGeneQ. For the same graph size (2^32 vertices, over 4 billion), that team delivered 4.4x higher performance – but also using more than 10 times the compute nodes and 17 times the cores. Although some of this is due to architectural differences, much of the reason for Intel’s improved per-core efficiency was in the algorithmic optimizations from our researchers.

The team in Intel Labs is excited to be among the world-class researchers tackling this new challenge.

To make this vision a reality, the ISTC for Pervasive Computing brings a uniquely qualified team of academics from top US universities together with Intel researchers to conduct research and guide this nascent field. The center is co-led by Prof Dieter Fox from the University of Washington at Seattle and Intel Principal Engineer, Anthony LaMarca. The center participants include other UW faculty, and professors from several top-tier schools (Cornell, Georgia Tech, Rochester, Stanford, and UCLA). Together with their bright young students, these thought leaders have laid out an exciting bevy of applications-based research topics. These are organized into the following ISTC-PC themes: 

- Low Power Sensing and Communications: Enable continuous unobtrusive awareness of people for long periods of time by adapting a system-level approach to power management including energy harvesting from ambient sources. 

- Understanding Human State and Activities: Recognition of the context of a user’s interactions with other people, smart objects and sensors in the environment. And get this, all in real time. 

- Personalization and Adaptation: Continuous learning of user’s preferences and adapting to new activities. 

These technology themes are essential building blocks to enable the pervasive computing applications of the future. Great thing about this center is that realistic scenarios from everyday lives will be used to drive the research. More concretely, following are the 5 projects that the ISTC-PC researchers plan to focus on: 

1. Mobile Systems for Improved Health and Wellness: Most peoples’ lives have fairly predictable daily patterns and activities. This project aims to develop mobile systems that are able to learn the user’s routines and goals using a variety of sensing platforms. Using stress sensing modalities, it aims to help users manage stress in their lives, and improve their overall well-being. 

2. Learning and Labeling Family Routines: Modern living is adding new complexity around family coordination, scheduling of activities, and interaction amongst family members. This project aims to track and understand these routines. 

3. Pervasive Perceptual Activity Sensing Infrastructure: This project aims to develop human activity sensing infrastructure that is capable of perpetual operation, using power harvesting from ambient sources. 

4. Task Assistance and Learning in Smart Spaces: Are you stumped by the complex set of instructions with tens of small parts like in assembling a home office furniture set, or making a cheesecake? Wish there was a guide alongside watching and advising, and suggesting a solution if you are stuck. This project will create local task spaces capable of helping users with physical tasks, by combining the user’s context, gestures, and voice inputs, and helping them complete a multi-step project. 

5. Understanding Objects, Scenes and People in Activities: This project will research computer vision-based approaches to enable rich and robust recognition of objects, scenes, and human actions in the context of daily activities. 

One key aspect of this research funding from Intel is that it is open and truly collaborative and all IP will be dedicated to the public. The idea is to conduct research and foster an ecosystem that encourages new computing paradigms with new usages which have the potential to make a large societal impact. 

Who knows, in the not so distant future we may have homes with walls and countertops that just do the right thing – facilitate our cooking, help organize and coordinate family activities, or sense our bad day at the office and welcome us home with soothing music. I am really looking forward to the exciting new developments at the ISTC for Pervasive Computing.

As part of the ongoing commitment in supporting research at Universities, Intel has contributed over $1M to support top PhD students across the nation for 1 year of their research. The Intel PhD Fellowship Program is a very competitive process where students must first be pre-selected by their universities to be able to apply for the fellowship. Each selected student submits a thorough application which is reviewed by Intel Fellows and senior technologists who choose the winners. This is a very prestigious award, and winning students are all leaders in their field and come very highly recommended by their university and/or industry partners. 

The fellowship program was started in the early 90′s by Gordon Moore to recognize and honor top students for their leading edge research in areas that would benefit the mankind; it was open to all fields of research. Gordon wanted to give back to those universities and communities who excelled at producing the top students. It was a way to build long lasting relationships with these universities, the professors and help create the next generation of technology leaders. The program has been supported every year for nearly 2 decades. Today’s program keeps that focus and also places an emphasis on developing students who are well aware of issues facing the Semiconductor, High Tech/IT fields. Every winning student is assigned a technical mentor in Intel who is also a leader in their field. Students are encouraged to work through their mentor and develop a deep, understanding of the technical issues facing the industry and be on the forefront of solving the technical challenges that lie ahead. 

This year, 21 fellowships were awarded. All of the winning students were invited to Intel in Oregon for the PhD Fellowship Forum. During this forum, the students were able to meet and hear lectures from top technical leaders across the company including Limor Fix, Vida Ilderem, Mike Mayberry, Kelin Kuhn, and many others. They also attended a networking dinner with many of the speakers as well as other Intel Fellows and Senior Principal Engineers. Intel is very proud to announce the list of this year’s winners – Congratulations to each one of you!!! 

Check out this video for highlights of the event. 

Don’t get me wrong, commodity DRAM processes are amazing feats of modern technology. DRAM process technologies incorporate the ability to hold massive memory capacity within a tiny piece of silicon all at an amazingly low manufacturing cost. However, with this exceptional memory density and cost structure brings limits on logic density and I/O performance; an area in which logic process technology optimized for a CPU really shines. We knew that future high-speed memory will need to conquer a challenging set of tradeoffs and achieve low cost and power as well as high density and speed. We came to the conclusion that mating DRAM and a logic process based I/O buffer using 3D stacking could be the way to solve the dilemma. We found out that once we placed a multi-layer DRAM stack on top of a logic layer, we could solve another memory problem which limits the ability to efficiently transfer data from the DRAM memory cells to the corresponding I/O circuits.

Getting the data out of the memory cells to the I/O is analogous to the difficulty of navigating the streets of a crowded city. However, placing the logic layer underneath the DRAM stack has a similar effect to building a high-speed subway system underneath the streets, bypassing encumbrances such as the DRAM process as well as the routing restricted memory arrays. Additionally, the adjacent logic layer enables integration of an intelligent control logic to hide the complexities of the DRAM array access, allowing the microprocessor memory controller to employ much more straightforward access protocols than what has been achievable in the past.

The result of this joint research project between Micron Technology and Intel has been the development of some key achievements. Last year, Intel designed and demonstrated an I/O prototype that achieved a record-breaking 1.4 milliwatts per gigabit per second energy efficiency that was optimized for this hybrid-stacked DRAM application. The two companies worked together to jointly develop and specify a high-bandwidth memory architecture and protocol for a prototype that was designed and manufactured this year by Micron. This hybrid-stacked DRAM prototype, known as the Hybrid Memory Cube (HMC), is the world’s highest bandwidth DRAM device with sustained transfer rates of 1 terabit per second (trillion bits per second). On top of that, it is also the most energy efficient DRAM ever built when measured in number of bits transferred versus energy consumed. This groundbreaking prototype has 10 times the bandwidth and 7 times the energy efficiency than even the most advanced DDR3 memory module available.

These developments will likely have a fundamental impact on data centers and supercomputers that thirst for low-power high-bandwidth memory accesses. With this technology, next generation systems formerly limited by memory performance will be able to scale dramatically while maintaining strict power and form factor budgets. Additionally, these developments may play a key role in the optimization of system architectures and memory hierarchies of future mainstream systems in the client and server markets.

The purpose of this chip is to advance near-threshold voltage (NTV) computing and to demonstrate the energy benefits of NTV designs, which promise better energy efficiency. Most digital designs operate at nominal voltages – about 1V today. NTV circuits operate around 400-500 millivolts – very close to the “threshold” voltage at which transistors turn on and begin to conduct current. It is challenging to run electronics reliably at such reduced voltages. To put it simply, the difference between a “1″ and a “0″ in terms of electrical signal levels become very small, so a variety of noise sources can cause logic levels to be misread, leading to functional failures. The benefit, however, is that energy consumption reaches an absolute minimum in the NTV regime with a sizeable ~5-10X improvement over nominal operation. The key challenge is to lock-in this excellent energy efficiency benefit at NTV while mitigating performance loss.

Several years of research went into realizing our first NTV IA Processor. Extreme sensitivity to power supply and transistor threshold voltage variations complicates NTV design. We had to develop NTV-aware techniques to improve design robustness for reliable operation. We re-designed the on-die caches and logic and incorporated new circuit design techniques and methods to tolerate variations at NTV, while increasing the chip’s dynamic operational range. For this test case, we picked one of our crown jewels – our first super-scalar Pentium core, though the same techniques could be applied to any Intel digital designs in the future.

The result is a “heat-sink free” processor core that can be placed in NTV mode at <10mW with minimum-energy and 5X better energy efficiency. The processor also provides wide dynamic operational range and can run at higher frequencies (~10X) when performance is needed. The new “always-on” – yet “ultra low power state” can keep applications running and is ideal whenever compute demands are modest. While this prototype may not become a product itself, conclusions from the NTV research could lead to the integration of scalable NTV technology across a wide range of future products from mobile to HPC.

NTV technology isn’t just unique to processors. The concepts are promising to a wide range of digital platforms and opens up many new “use conditions”, taking “always on” to a new level. For instance, this could be compelling for smart phones, tablets and other devices allowing “one” design to efficiently scale all the way, obviating the need for heterogeneous architectures. Also, these ultra-low power levels could allow Intel architecture to expand into broader applications like embedded devices, which would include “everyday” devices such as home appliances and automobiles.

In fact, one goal of NTV research is to enable “zero power” architectures where power consumption is so low that we could power entire digital devices off solar energy, or off of the energy that surrounds us every day in the form of vibrations and ambient wireless signals. This gives us unfettered freedom so we can just leave our power cord and chargers behind. NTV research is particularly applicable to self-powered autonomous sensor networks and monitors strewn about our environment allowing computers to “see” and intelligently “react” to the world around us.

Finally, Justin’s keynote highlighted that NTV research is quickly maturing and the processor is a key enabler for Extreme Scale Computing. Extreme scale means getting the most energy-efficient performance for the power spent – achieving 1000x performance at only 10x the power, or perhaps 10x performance at 1/10 the power. This could help us realize massive Exa-scale supercomputers or put trillions of computations per second in our pockets, while being environmentally-aware.

Way!

If applications were like road traffic, then web browsers used to be the country roads: Capable of handling some traffic at slow speeds but too underdeveloped to take a heavy load. This no longer is the case. Browser vendors have invested into their browser’s execution engines, increasing the speed limit on their country roads significantly. Still, native applications have a performance advantage.

This advantage is no longer just due to slower execution speeds. If you look at modern processors, they all come with some form of vector extensions that allow the processor to execute multiple operations at the same time. Keeping with the road analogy, native applications run on multi lane highways. Intel’s 2nd generation Core series just introduced AVX, which doubled the number of lanes compared to previous processor generations. Another performance boost available to native applications is the use of multiple roads: Most modern systems feature a multi-core processor.

Web applications so far have lost out in both regards. JavaScript, the language behind the web, does not give applications access to multiple cores, let alone vector instructions. Thus forcing me to use native applications where performance matters although I would prefer staying in the browser. Clearly, it is time for JavaScript to catch up.

This is where Parallel Extensions for JavaScript, code named River Trail, an Intel Labs project I am working on that is currently shown at IDF, comes into the game. River Trail brings the processing power of Intel’s multi-core CPUs and their vector extensions to web applications. With River Trail it will finally be possible to stay in the browser even for more compute intensive applications like photo editing.

What really excites me about the technology behind River Trail is its seamless integration with existing web technologies. River Trail extends JavaScript with a simple, yet powerful data-parallel programming model. Much effort was spent to make this extension feel as natural as possible. Our goal was to make writing web applications with River Trail as easy as writing regular JavaScript. Furthermore, as River Trail is embedded into JavaScript, it combines well with other upcoming HTML5 APIs. We in particular made sure that River Trail plays nicely with WebGL, a recently introduced JavaScript API to OpenGL used for 3D visualization in the browser: One of our demo applications is a physics simulation with more than 4000 bodies, where the computation is done using River Trail and visualization is performed with WebGL.

Bringing new technologies to the web immediately raises the question of their impact on the user’s safety. This is true for River Trail, as well. The web browser, by its nature, is on the front line of attack. JavaScript code, whether extended by River Trail or not, is loaded from remote systems that are outside of the user’s control and is executed on the local machine. Protecting the user from abuse and ensuring the security of River Trail therefore were major concerns in the design. River Trail was designed to inherit the security traits of JavaScript and I am confident to say that our extensions to JavaScript do not add any further attack surface to the browser.

Will River Trail be the end to native applications? Probably not. Will it lead to improved web applications and new kinds of usages for the web browser? Hopefully so! River Trail is available todayas an add-on to the Firefox web browser. You are invited to join us and refine it, make use of it, change the web. We have built a computing high-way for the web browser. Let’s make use of it.

We would like to utilize Intel Developer Forum (IDF) as an opportunity to introduce to you the latest advancements in our 3D web project and please do stop by Intel Labs Pavilion to interact with the 3D web.

For the 3D Web, the first task is to define a method how to “code” 3D scenes. Here, the IVCI approach is a declarative one – our XML3D language describes all components of the scene, including the 3D objects, their positions and transformations, textures and surface properties, shaders, lights and cameras. XML3D is based on XML and fits very nicely into HMTL5 – all the scene components become parts of the HTML domain object model, exactly like text, 2D graphics and videos today. And, all the established ways of “Web programming” naturally extend to the 3D scenes – it is, for instance, extremely simple to change the position of a 3D object from Javascript, and flying that spaceship along a trajectory is straightforward. And, the color and surface properties can be changed via CSS, with zero programming effort involved.

Procedural approaches like WebGL do require deep knowledge of graphics programming (like OpenGL) that is not normally available with Web content developers and programmers. XML3D does not require any new (to a Web developer) programming skills – only knowledge of content creation tools that help to create the scene description.

On the client side, the IVCI team has produced extensions to the Firefox and Chromium browsers that parse the XML3D language and render the 3D scenes in a browser window. The beauty of a scene description (rather than an OpenGL program) is that the browser can select the right rendering method for any given device, and the same scene description will look best on a wide range of devices. Our prototype browser extensions support a highest quality ray tracing renderer, WebGL and OpenGL ES.

At IDF, we are showing end to end demos of a 3D shopping experience, a virtual museum and a car configurator. You can find us in the Intel Labs pavilion, booth 5080 in the exhibition hall.

Complete information about the 3D Web project can be found on http://www.xml3d.org.

Looking at the next generation of wireless technologies, here at Intel, we are searching for disruptive methods to add network capacity with a focus on greater efficiency in multimedia content delivery that enhances user experience. Amongst the key technologies under research are: 1) optimized compression of video content to reduce network traffic, 2) intelligent aggregation of capacity across multiple radio networks, and 3) video quality aware optimization for wireless network.

At the 2011 Fall IDF, we are showing a demo [Scalable Video Over Multi-Radio Networks] that illustrates the gains possible by combining these technologies. We employ optimized video compression with Scalable Video Coding (H.264 SVC) to establish different resolutions: a base layer, which provides a baseline level of video QoE; and one or more enhancement layers that build upon the base layer with increasing levels of quality of experience (QoE) – in any combination of temporal, spatial, or picture quality dimensions.

We then show how content delivery is judiciously balanced over different radio networks (cellular and WiFi). While the base layer is continuously transmitted over cellular, the enhancement layers are opportunistically delivered when available capacity is present at WiFi hotspots, providing the user with better quality of video. Figure below illustrates this concept. The advantage for service providers is that this offers a way to balance load across different kinds of spectrum – licensed/unlicensed, WAN/LAN, etc. For users, the benefit is a flexible, or scalable QoE based on their local access to different spectrum bands.

As additional eye-candy we included several post processing special effects (thanks to Ben Segovia). Just to clarify: those are not specific to ray tracing and have been seen in some games already. They are operating on the pixels of the rendered image (not on the 3D scene) – in our case directly on the Knights Ferry card. They can improve the perception of the rendered scene dramatically.

• Depth of Field: The effect is well known to photographers. If we want the spectator to focus on a certain area in the picture then the less relevant parts can be blurred. Therefore the object of interest is still sharp and will attract the main attention.
    

  Depth of field on/off (3% performance difference)

• HDR Bloom: If in reality we leave from a dark room into the bright outside our eyes are adjusting over a few seconds to the new brightness. The same can also be observed with digital (video) cameras that mimic this behavior and adjust the brightness spectrum to a pleasantly looking image. While doing this cameras might produce a bloom that can also “bleed” into other objects.
    

  Overbright scene with HDR on/off (2% performance difference)

   

  

   

  Bloom effect

   

• Inter-lens reflections: While camera manufacturers are trying to avoid lens flares computer games and movies are often adding them as an artistic element. In this implementation several smaller sized version of the image, shifted to a specific color (e.g. green, blue and orange) will be blended into the original image.
•   Subtle (image-based) inter-lens reflections (0.1% performance difference)

Another step we are doing for the first time is a smart way of anti-aliasing (thanks to Ingo Wald and Ben Segovia). There are different possibilities on how to do anti-aliasing. Most of them work pretty much brute-force and therefore invest additional calculations in areas where the improvement might not be noticeable. Our implementation will be applied after the image has been rendered. As ray tracing easily allows to just shoot a few rays for refinement we are analyzing each pixel depending on two factors if it requires more anti-aliasing:

• The angle of the polygon that got hit at that pixel
• The polygon mesh ID of that object

If there is a high enough variation in the angle or a different mesh ID is found we will shoot 16 more rays (supersampling) for that specific pixel and average the resulting color into that pixel. (Please note that the difference can be seen best in the full-sized images that appear after clicking the thumbnails.)

Courtyard view: Smart Anti-Aliasing off

Courtyard view: Smart Anti-Aliasing on (59% performance difference)

Close-up on cable: Smart Anti-Aliasing off

Close-up on cable: Smart Anti-Aliasing on (32% performance difference)

For future implementations more criteria like the color of the pixel (e.g. imagine an almost black spot in the picture – aliasing will not be noticeable here) or the color between neighboring pixels could be added. Further before comparing those colors MLAA could be used to reduce aliasing first and then later only certain areas could be refined through shooting new rays. Tweaking the numbers of additional rays to 4 or 8 might lead to better performance/quality tradeoffs.

We would be happy to show you the real-time demo at IDF at the Intel Labs pavilion, booth 5080 in the exhibition hall.

Additional thanks to Ram Nalla, Nathaniel Hitchborn, Sven Woop, Alexey Soupikov, Alexander Reshetov.

The system that can hold the eight double-sized PCI-Express cards has been provided by Colfax International to us. Thanks!

Come hear Manfred Ernst discuss Monte Carlo ray tracing kernels as well as an overview of the sample renderer at SIGGRAPH.

Room 216 from 10:45-11:45 AM. Wednesday, August 10th

Visit http://www.intel.com/software/siggraph for more information and to view the presentation slides.

Intel’s 2nd Generation Intel® Core™ Processors are great at handling ray tracing. To get a good look at the images Embree can create, go to http://software.intel.com/en-us/articles/embree-photo-realistic-ray-tracing-kernels/. Download the source code from this page and soon you could be rendering realistic 3D images of your company’s products, displaying a walk-through of an architectural model, or creating jaw-dropping images for your films, games or advertisements.

Find out more about Intel Labs’ Visual Computing Institute.

Room 216 at 9:00 AM – 10:00 AM Wednesday, August 10th.

Swing by Intel Labs’ Visual Computing Booth #329 and you could be chosen to win a free Intel SSD!

]]> http://blogs.intel.com/intellabs/2011/08/08/create_photorealistic_3d_model/feed/ 0 http://blogs.intel.com/intellabs/2011/08/03/istc-call/ http://blogs.intel.com/intellabs/2011/08/03/istc-call/#comments Wed, 03 Aug 2011 07:50:00 +0000 http://blogs.intel.com/research/2011/08/03/istc-call/ Read more >]]> Intel is a major sponsor of academic research all over the world. We support research in many academic fields ranging from silicon technology to cloud applications. In most of our engagements with academia we contribute more than funds and equipment, that is, we establish an open dialog and exchange of research challenges and ideas among Intel leading technologists, faculty and students.

My team, called Academic Programs and Research, is supporting academic research using several different programs. Some programs are more directed and aimed at solving a specific technology bottleneck (details by our Academic Research Office in http://techresearch.intel.com/ThemeDetails.aspx?id=10). Other research programs, have wider span and are aimed at advancing the state of the art in research areas of growing importance to the consumer and the IT industry. Recently, we have identified several such research areas: visual computing, secure computing, cloud computing, embedded computing and pervasive computing. To accelerate innovation in these areas, we have already launched in recent months four research centers, called Intel Sciences and Technology Centers (ISTCs). Each such center, is hosted in a leading US university and it includes several additional universities. Our vision is for a center to build the best research community to advance the selected research topic. This community will encompass a large group of faculty and students, thoughts leaders and researchers from Intel and, likely, additional sponsors and participants from industry and government. We want this community to work together, to ignite each other innovation and to march toward common research goals. The mix of researchers from Intel, which have hands on the leading industrial technology and knowledge of the market together with young and brilliant students and faculty from several diverse university research groups is very promising and this what we are after. Intel Science and Technology Centers are operating in an open IP model. All research results will be published and all significant software will be released open source. We believe that the openness of the IP Model is important for enabling cooperation and for achieving the maximum progress in the chosen research area to the benefit of all consumers and Intel’s customers.

On Aug-3 2011, we have announced an open call for abstracts in which we are inviting faculty from US universities to submit an abstract of a proposal for a new ISTC. We are inviting the academic community in the US to help us identify additional areas of research that, on the one hand, have potential to make important impact on end-users and businesses and, on the other hand, are on the verge of technology breakthrough and new game changing capabilities.

Faculty and students involved with Intel Science and Technology Centers are gaining both additional funds to support their research and the opportunity to make an impact on the real world with their inventions. The road from good ideas to end-products is usually long and hard and many excellent technologies never make their mark on the world due to this challenge. I strongly believe that the ISTC model of collaboration between industry and academia will dramatically strengthen the pipeline of technologies from academia to industry and will benefit the US economy. I have already attended several workshops and events organized by the Secure Computing ISTC hosted by University of California, Berkeley and the Visual Computing ISTC hosted by Stanford University. The energy level, the openness, the amount of new ideas and the number of new collaborations was heart-warming.

Do not delay and submit your suggestion before 11:59pm PDT, September 2, 2011. For more details see http://intel.com/go/istc-abstract

]]> http://blogs.intel.com/intellabs/2011/08/03/istc-call/feed/ 0 http://blogs.intel.com/intellabs/2011/08/02/istc-cmu/ http://blogs.intel.com/intellabs/2011/08/02/istc-cmu/#comments Tue, 02 Aug 2011 07:50:00 +0000 http://blogs.intel.com/research/2011/08/02/istc-cmu/ Read more >]]> Imagine leaving the office carrying a briefcase full of work. As you enter your car, the updated family calendar is shown on the dashboard display. With anticipated free time for the new few hours before you get the kids, you stop by the shopping mall along the route home. At the entry to the mall, you pause in front of a digital sign that recognizes you and displays products of interest.

A virtual assistant engages you in a brief conversation and then directs you to the store(s) carrying the clothes and shoes you need. It also sends a 20%-discount coupon to your smart phone –another of the many bargains you have received since allowing the mall’s networked-sensor system to gather information and learn about your interests.

Driving home, the vehicle taps into vehicle to vehicle (V2V) sensor network that is processed through the cloud and provides up to date routing to avoid traffic and weather/road based hazards to pick up the kids and get home safely.

When you arrive home, you are greeted by the family’s robot-maid Zia who begins preparing a stir-fry dinner based on knowledge of what the family members had for lunch, what’s currently in the refrigerator, and what ingredients/dinners they have enjoyed in the past. As the robot pulls ingredients from the fridge, the grocery shopping list is updated automatically. A side panel shows an up to date calendar and real-time information about the location of family members to align dinner time with their arrival. You check on the progress of dinner. Because the Zia still can’t cut shiitake mushrooms proficiently, you cut them instead and explain the technique. Zia records multi-sensory input of your actions for later analysis and learning.

Fiction? Today….maybe. In the near future…not at all. Some of the technologies needed to support the above scenarios are in the nascent stage while others still need to be explored. How soon to reality? No one knows for sure but one thing we do know; They all require a tremendous amount of computing resources and open the possibility for new markets and applications for our products. But how do we get there from where we are today? Well that brings me to Intel’s announcement of two new Intel Science and Technology Centers(ISTCs) which will perform research and explore areas to provide a foundation to make these scenarios a reality someday. The two centers will be focused on cloud computing and embedded computing and will be co-located at CMU. This is part of Intel’s strategy of funding high impact research centers at universities. In fact, Intel has committed $100M in funding over the next 5 years to support this endeavor. With two ISTCs centers already having been announced (the Visual Computing Center located at Stanford and the Secure Computing Center located at UC Berkeley) we want to welcome their two sister centers to the fold.

Three unique features designed to increase the probability of successful collaboration are a part of the fabric of the ISTC. They are (a) an open collaborative research model which encourages all researchers under the ISTC umbrella to release their results into the public domain creating an open IP model (b) a multidisciplinary approach which means the complete platform is explored (both HW and SW) across multiple engineering disciplines creating an integrated approach to research and finally (c) the “Hands-on” involvement of Intel. Each “Hub” school will provide an academic principal investigator(PI) to work alongside a counterpart PI from Intel. Additionally, Intel labs will provide up to three researchers co-located with the center in addition to the Principal investigator to ensure close (“Hands On”) collaboration with Intel as well as creating a natural technology transfer conduit when the ISTC ends and the embedded resident researchers are assimilated back into the labs on an Intel campus.

“Seeding” the Clouds

The cloud computing center focuses on enabling new paradigms to make cloud computing of the future more efficient and effective. For instance, broadcasting texting and tweeting does not require the same amount of computing power as video compression and streaming. Yet today, we provide the same amount of computing power to handle both making homogeneous based computing centers energy inefficient. We expect the amount of data handled by cloud centers of the future to only get larger. Large amounts of data require the exploration of Big Data analytics as we seek to efficiently process and stream various data content. As these data and processing centers grow, more automation will be required to facilitate IT support. With this in mind, the ISTC Cloud Computing center will have four main thrust areas:

Specialization: Contrary to the common practice of striving for homogeneous cloud deployments, clouds should embrace heterogeneity, purposely including mixes of different platforms specialized for different classes of applications. This pillar explores the use of specialization as a primary means for order of magnitude improvements in efficiency (e.g., energy), including new platform designs based on emerging technologies like non-volatile memory and specialized cores.

Automation: Automation is key to driving down the operational costs (human administration, downtime induced losses, and energy usage) of cloud computing. The scale, diversity, and unpredictability of cloud workloads increase both the need for, and the challenge of, automation. This pillar addresses cloud’s particular automation challenges, focusing on order of magnitude efficiency gains from smart resource allocation/scheduling (including automated selection among specialized platforms) and greatly improved problem diagnosis capabilities.

Big Data: Cloud activities of the future will be dominated by analytics over large and growing data corpuses. This pillar addresses the critical need for cloud computing to extend beyond traditional big data usage (primarily, search) to efficiently and effectively support Big Data analytics, including the continuous ingest, integration, and exploitation of live data feeds (e.g., video or twitter).

To the Edge: Future cloud computing will extend beyond centralized (back-end) resources by encompassing billions of clients and edge devices. The sensors, actuators, and “context” provided by such devices will be among the most valuable content/resources in the cloud. This pillar explores new frameworks for edge/cloud cooperation that (i) can efficiently and effectively exploit this “physical world” content in the cloud, and (ii) enable cloud-assisted client computations, i.e., applications whose execution spans client devices, edge-local cloud resources, and core cloud resources.

The center brings together top academic minds from CMU and three other top tier US Schools(UC Berkeley, Georgia Tech, and Princeton). The academic PI is Professor Greg Ganger (CMU) while his counterpart from Intel is Principal Research Scientist Phil Gibbons. Along with them, there will be 21 academic researchers and 3 Intel embedded researchers.

Embedded Computing

The ISTC-EC center brings together thought leaders from seven different universities (CMU, Georgia Tech, UC Berkeley, University of Illinois at Urbana-Champaign, Penn State, University of Pennsylvania, and Cornell) to drive research and transform experiences in the Retail, Automotive and Home of the future. The popularity of real-time intelligent and personalized technology is growing and the demand for specialized embedded computing systems will correspondingly grow to support a broad range of new applications — many yet to still be envisioned. The ISTC Embedded Computing Center will have four main thrust areas:

Collaborative Perception: Perception in embedded applications has unique challenges as it must be performed online and in real-time in the face of limited power, memory and computational resources. The Collaborative Perception theme seeks to explore new ways to do this robustly.

Real-time Knowledge Discovery: Machine learning in embedded applications carries with it a host of unique challenges: low-power environments, multiple specialized sensing modalities, complex tradeoffs between pushing computation to the cloud or first processing data locally, and efficiently incorporating vast quantities of local/external data into local computations, etc.

Robotics: Robotic toys and vacuum cleaners are starting to inhabit our living spaces, and robotic vehicles have raced across the desert. These successes appear to foreshadow an explosion of robotic applications in our daily lives. However, without advances in robot manipulation and navigation in human environments, many promising applications will not be possible. We are interested in robots that will someday work alongside humans; at home or in the workplace.

Embedded System Architecture: The Embedded System theme aims to realize large-scale algorithms such as real-time learning and collaborative perception efficiently, given the unique power, memory and computational resource constraints of embedded systems, the particular context (physical location, proximity), as well as the domain-specific requirements.

The center will have two PIs, Priya Narasimhan (associate professor at CMU) and Mei Chen (Intel Labs Research Scientist), driving research and collaboration across the various institutions. Along with them, there will be ten leading researchers from the universities listed above along with 3 Intel embedded researchers and 2 additional embedded researchers from ECG.

The future is bright. Let’s keep moving forward.

]]> http://blogs.intel.com/intellabs/2011/08/02/istc-cmu/feed/ 0 http://blogs.intel.com/intellabs/2011/07/11/cant_wait_to_create_photo-real/ http://blogs.intel.com/intellabs/2011/07/11/cant_wait_to_create_photo-real/#comments Mon, 11 Jul 2011 11:44:24 +0000 http://blogs.intel.com/research/2011/07/11/cant_wait_to_create_photo-real/ Read more >]]> After witnessing the visual computing research demos at Research at Intel Day 2011, I am excited to envision consumer shopping experience in the near future. Actually the “near” future is going to be nearer than I thought because Intel Labs announced that it will release “Embree: Photo-Realistic Ray Tracing Kernels” as open source. This will enable people (yes, literally anyone) to try out the code and use it for free if they like it.

Embree is a progressive photorealistic rendering system that turns 3D models into images that are virtually indistinguishable from a photograph. Viewing 3D models as images is part and parcel of daily consumer life. Online shopping, movie production and architectural visualization are very good examples where realistic rendering of 3D models is important. Turning 3D models into pictures can be done in three ways. Non-interactive, real-time and progressive methods. Briefly the differences between these methods are

- Non-interactive: Images are pre computed and stored for later viewing. (Example: Movie production)

- Real-time: Used in dynamic interactive environments where it is impossible to predict the image to render. The 3D model must be converted to images on the fly and latency cannot be tolerated in such environments (Example: Games)

- Progressive: An interactive scene can be converted to an image but slight latency can be tolerated (within seconds). A final image which is virtually indistinguishable from a photograph will be rendered in few seconds. This method can be viewed as intermediate between Offline (which takes hours or sometimes days) and real-time.

Professionals such as movie makers, architects, and car companies currently use non-interactive methods to create photo-realistic images for consumers. Software develops can use the Embree photo-realistic ray tracing kernels to improve the performance of their rendering applications by as much as 2X, accelerating the transition from non-interactive to progressive rendering.

This transition will enable completely new applications and user experiences. Imagine being able to walk thru a newly-designed building online before it is built and being able to get photo-realistic pictures from arbitrary view points within seconds, or being able to see an accurate 3D model of your new car headlights before you order it.

Read about Embree, see a demo, and download the source at: http://software.intel.com/en-us/articles/embree-photo-realistic-ray-tracing-kernels/. I can’t wait to hear your experiences.

To solve the problem, Intel has created a new way to construct virtual environments.

Basically, they break down all of the important jobs that a server has to do in order to run a virtual world. For example, all of the client connections can run on one group of servers, while scripted object behaviors and physical simulation (e.g. gravity, motion and collisions) are each running somewhere else. The users then interact on what’s called a “Distributed Scene Graph”, the intersection of all of these various constituent parts. This compilation can scale to allow for the needs of the application or event. If you need more detailed surroundings (like the one below), you won’t have to sacrifice script complexity or the number of interacting elements.

Similarly, you could populate a space with thousands of users without crashing the whole world. By separating the individual functions that compose a virtual world, each job can be allocated the proper amount of resources without taking away from the other functions.

So, if you want to throw a concert, you could set up the stage and the performers on one service provider so that the immense throngs of adoring fans won’t interfere with the show. Alternatively, scientists could collaborate on complex operations using intricate models. Then, these models could be used to educate hundreds of thousands of college students in a virtual lecture hall or a programmed archeological dig.

Maybe the fact that Intel can pull off increasingly complex environments with only a fraction of the processing power for the scene doesn’t impress you. If not, perhaps the fact that they are open-sourcing this new technology will. To read more about distributed scene graph, or to see a demo, or download the code for free visit http://software.intel.com/en-us/articles/scalable-virtual-environments/

At this booth, I got an overview of visual computing research centers and its focus area with some cool demos. These centers create a community of researchers across US and Europe to drive visual computing research ground work for next generation visual computing applications. The two visual computing centers:

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Intel visual Computing Institute (Leaders across Europe) at Saarland is focused on 3D internet, Bridging Real and Virtual Worlds and Scalable Rendering

Intel Scientific and Technical Computing for Visual Computing (ISTC-VC) consist of leaders in visual computing across US and is focused on content creation, real-time scalable simulations, perceiving people and places.

Among all these focus areas; the center is also looking at underlying hardware platforms that are going to allow the applications to run affectively in the next few years.

These two centers are building community that in combination can drive visual computing technology development in many ways to improve user experience. Intel will inject latest and greatest innovations into Intel and then go through revisions and finally find a way into products to provide the experiences the users really want!

By the click here for more information

Visual Computing Zone:

Personal Energy Zone:

Cloud Zone:

Most new cars now have support for digital media, Bluetooth and USB device connectivity; some even have internet and WiFi on-board. However, having just sampled the currently shipping systems from some of the world’s leading car manufacturers, I can say firsthand that the feature lists and capabilities are very extensive and impressive, but there is room to dramatically enhance and innovate on the experiences they deliver. You can, in fact, connect your phone, play digital media, and access some connected services. All, after spending a significant amount of time connecting devices, setting up accounts and passwords, and finding controllers and buttons. Unfortunately, getting the most from these systems requires a significant learning time and reading user guides. One vehicle benchmarked had 3 system displays, 4 rotary controllers, and a touch-pad that must be used in conjunction with a multi-button rotary controller. Yikes! While I applaud the rapid integration of technology into vehicles, there is a lot of room to innovate on how these technologies are designed and integrated for the vehicle environment. The magic required is system level integration for the user’s tasks at hand, user design with a purpose. What tasks are users trying to accomplish most often, while simultaneously using the vehicle? How can these be made compelling experiences and not more work for people? Intel labs Integrated Platform Research is demonstrating how to combine the computing and communications capabilities embedded in the car, with that of smart phones and vehicle-focused cloud services. Bringing them together in a simple, compelling way. The Car, Cloud and Phone experience at Research@Intel securely connects these components with one touch. It leverages the deep processing and service capabilities of the cloud for customized vehicle remote control and video surveillance. With this technology in your new car you could quickly and easily pair your smart Phone with it, even before you drove it home from the dealer. Your phone would automatically be configured specifically for your car putting its unique features and controls at your fingertips, even when you are away from your car. Our app looks familiar, reproducing the look and feel of your car’s interior, key FOB buttons, displays, even the look of the dash. You can be away from your car, but stay in touch with it. Inside a restaurant ordering dinner? What happens if your car is bumped? You will instantly be notified on your phone. You’ll be able to view stored and live video from your car, directly on your phone. Someone’s pet bumped into your car?, No problem, enjoy your dinner. Another vehicle hit your car? No that’s a problem and you can take action. This is only one example of what you could do with your car, the cloud and your phone working together. This technology is fully integrated with a production vehicle and its embedded, on-board systems. I can’t wait to see people’s reaction to these new in-car and remote vehicle experiences.

]]> http://blogs.intel.com/intellabs/2011/06/13/intel_in_automotive_intel_labs/feed/ 6 http://blogs.intel.com/intellabs/2011/06/07/researchintel_2011/ http://blogs.intel.com/intellabs/2011/06/07/researchintel_2011/#comments Tue, 07 Jun 2011 23:09:20 +0000 http://blogs.intel.com/research/2011/06/07/researchintel_2011/ Read more >]]> We’ve just finished up with the 9th annual Research@Intel press event, at which Intel Labs showcased examples of forward looking research to media and industry analysts from around the globe. Intel CTO Justin Rattner kicked off the event by stressing the importance of collaboration between Intel, academia, governments, and the broad technology industry in order to turn the ideas of today into reality. He cited Intel’s collaboration with Apple to develop ThunderboltI/O technology, which had its genesis in Intel Labs as well collaborations with DARPA to develop extreme-scale computing technology 1000x more capable than what can be done today.

Justin also announced a new Intel Science and Technology Center (ISTC) for Secure Computing. This center will be co-led by Intel Labs and UC Berkeley and will research breakthroughs to make personal devices and data more secure. Berkeley will act as the hub of academic research for the center, which also includes researchers from University of Illinois, CMU, Drexel, and Duke. This is the second in a series of ISTCs to be announced this year – we announced the ISTC for Visual Computing, co-led by Stanford University, in January.

He also referenced the Many-core Applications Research Community, a network of more than 80 institutions testing next generation software ideas using the 48-core “Single Chip Cloud Computer,” a concept chip developed at Intel Labs. The learning from these research efforts will help guide the development of future architectures which are even better suited to the needs of tomorrow’s cloud datacenters.

The mood on the show floor today was exciting. I had the opportunity to give a livecast on the demos in the “cloud” zone describing projects such as a cloud-based, ray traced game running on handheld devices and a virtual city designed to for disaster response training. For the latter the innovation shown was the ability to scale the number of ‘players’ in such online, virtual training scenarios from hundreds to thousands. And, announced today, this code will be made available via open source for use by the OpenSim virtual world community later this month.

We also announced today that Intel Labs will open-source code for a different ray tracing project that targets offline, photorealistic rendering for uses such as design and digital effects in film. This code can provide up to a 2x speed boost for such professional applications and will also be available later this month.

In other parts of the show floor we showed an array of interesting projects: a bike powered netbook for developing economies, a “magic mirror” that allows you to see your virtual body and change it based on real human body scans, a programming system designed for exa-scale supercomputers of the future, human perception technologies, and more. Many of these projects include academic, industry and government collaborations of the type Justin emphasized in his opening address.

Looking around the event I was amazed at the diversity of projects, the number of leading minds in the room, and the level of interest in the research. And, as part of the R@I planning team I know that the ~35 demonstration on the floor represent only a fraction of the projects at Intel Labs. From here, the future looks bright.

Looking under the covers at the online touring demo, you can see that research at the Intel Visual Computing Institute into transparent 3D internet technology will allow 3D-like realistic viewing of online content without proprietary browser plugins. Intel’s latest processors provide the hardware support for very rapid rendering of realistic views of objects in the browser. However, Intel Labs didn’t stop there. They extended the improved visual experience to digital content by coupling Intel’s platforms with consumer electronic devices to provide a must-have user experience in our living room.

Intel realizes that it’s not all about shopping. Next generation virtual environments are impacting the gaming industry and becoming a ground for realistic test scenarios. Small businesses are now generating revenue using technologies based on virtual environments. What if we can add real-time technologies such as, facial and emotion recognition etc to virtual applications? What if today’s virtual world backend can support more than 20 times the avatars that are supported today in a virtual scene? This enables you to interact with virtual objects in many new and interesting ways for a much more realistic immersive virtual experience. A good example Intel Labs is showing at Research at Intel day is a massive multiplayer “game” to train first responders for different disaster scenarios. As part of its strategy to increase collaboration across the industry and the academic sectors, Intel Labs will release source code for its Distributed Scene Graph 3D Internet technology. This code is part of an ongoing effort to augment the OpenSim open-source virtual world simulator and will enable developers to build virtual regions where people can work or play online with a cast of thousands instead of being limited to less than a hundred today.

Finally, applications such as architectural visualization often require expensive propriety applications to create realistic computer models. Intel labs will release open source software which can be utilized by third parties to enable photo-realistic rendering of 3D models into 3D images that are indistinguishable from a photograph. This advanced ray tracing code targets professional applications and is a separate effort from our game-focused real-time ray tracing project shown previously.

Cool stuff, huh? Since there are over 40 demos planned, I’ve described just a very small sample of what will be shown to the press at Research at Intel Day.

I hope this quick peek behind the scenes has been interesting to you. As I learn more leading up to Research at Intel Days and attend the event, I will keep my thoughts coming on my blog. So stay tuned and don’t forget to check back with me for the live stream of the event as I walk through the visual computing research demos. The live stream will start on June 7th, 2011 at 1PM PST. Mark your calendars!

]]> http://blogs.intel.com/intellabs/2011/06/07/what_is_intel_doing_to_visuali/feed/ 0 http://blogs.intel.com/intellabs/2011/06/07/wolfenstein_gets_ray_traced_-_1/ http://blogs.intel.com/intellabs/2011/06/07/wolfenstein_gets_ray_traced_-_1/#comments Tue, 07 Jun 2011 10:00:00 +0000 http://blogs.intel.com/research/2011/06/07/wolfenstein_gets_ray_traced_-_1/ Read more >]]> Since the last entry on this Research Blog about the cloud-based Wolfenstein: Ray Traced demothere have been several enhancements.

The previous setup that required four separate machines each with one Knights Ferry card (Intel MIC) inside has been changed to a configuration where the cloud is represented by having a single server with four Knights Ferry cards. We showed this setup at CeBIT 2011.

This time at the Research@Intel Day 2011 we extended the setup to also work on Intel-powered tablets. We are demonstrating this on the Lenovo S10-3t (10 inch) and on the Viliv S5 UMPC (5 inch). Due to the lower screen resolution a cloud setup with one machine with one Knights Ferry per client is enough to feed the tablet at a frame rate of 20-30 fps.

Cloud-based gaming approaches could lead to a situation where it doesn’t matter where you are or which device you have to play your favorite game.

Further detail about the implementation and the benefits of using cloud-based ray tracing for games can be found in the paper “Experimental Cloud-based Ray Tracing Using Intel® MIC Architecture for Highly Parallel Visual Processing”.

The ISTC for Secure Computing center is embarking on an ambitious program to develop the technologies that seamlessly and automatically ensure the trust of the user in a variety of client and mobile devices and platforms. Simply stated – the research goal of the center can be summed by the acronym SCRUB, Secure Computing Research for User Benefit.

The center brings together top academic minds from UC Berkeley and four other top tier US schools (Carnegie-Mellon, Duke, Drexel, and University of Illinois) as well as four Intel researchers in a collaborative open IP environment. The center is co-led by Prof. David Wagner (UC-Berkeley) and John Manferdelli (Intel Senior Principal Engineer). These thought leaders supported by bright young students, have organized the SCRUB research into five thrusts, each addressing a key component of end-user security. The thrust areas are:

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Secure clients using a “Thin Secure Intermediation Layer”, providing partitioned and isolated software domains on a single device. This allows critical activities to run in a secure zone, while keeping “risky” activities in well-isolated relaxed partitions.

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Secure mobile devices from third-party apps by developing tools to build and validate the safety of these apps. Provide a simple permissions system for users that enables safe use of third-party apps across business and personal environments.

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Secure data storage, transmission and use that guarantee the safety of user-data regardless of where it is moved and used, while preserving the user intent. Develop a data encapsulation and safe use policy system.

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Secure network architectures enabling scalable global monitoring of application semantics, while assuring data confidentiality for the individual user.

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Secure analytics by learning how to detect adversarial activity, and develop models and tools for measuring, tracking and analyzing the flow of information

An important outcome from this effort will be to bring together a community of academics in partnership with industry colleagues to nurture the growth of critical thinking in the secure computing arena. This means publishing research results, growing the next generation of technical leaders by training the next generation of students, and providing the basis for new business opportunities for new products and services in ways not yet imagined. Not only has Intel provided funding for the center but it has significantly simplified research collaborations and amplified the potential impact of the center by encouraging an open IP model.

I believe that the ISTC-SC research thrusts together form the key components of security and trust concerns on end-user clients and mobile devices. I am looking to the day when I can install an app, manage financial records, and communicate with friends and business colleagues from my home client devices to the smartphone, all safely. Yes, I am one of many users in a digital future who stand to benefit from the research of the new ISTC on Secure Computing.

]]> http://blogs.intel.com/intellabs/2011/06/07/istc-sc/feed/ 1 http://blogs.intel.com/intellabs/2011/05/04/mario-ace/ http://blogs.intel.com/intellabs/2011/05/04/mario-ace/#comments Wed, 04 May 2011 08:00:00 +0000 http://blogs.intel.com/research/2011/05/04/mario-ace/ Read more >]]> I’m writing today to congratulate Intel Fellow Dr. Mario Paniccia for receiving EE Times’ “ACE” award for Innovator of the Year last night in San Jose. These awards celebrate technologists who demonstrate leadership and innovation to change the electronics industry and the world. He won this for leading the research team that developed the 50Gbps Silicon Photonics Link, a concept fiber-optic connection designed to validate Mario’s vision to ‘siliconize’ photonics.

This device represents a tremendous potential to bring fiber optics to the mainstream. For personal devices, it could become practical to have connections that could backup an entire hard drives or transfer entire music libraries between devices in seconds. A single cable could carry video to a wall-sized HD display with a resolution equal to an array of ten or more 1080p screens. For the enterprise, pervasive fiber optics could eliminate traditional design constraints due to the distance and bandwidth of data cables. Entirely new architectures could be created which rearrange CPUs, memory, and other devices in a much more scalable fashion.

Though this is his first ACE award, it is actually the second time Mario has been nominated The first was in 2006, following the development of first 1 GHz silicon modulator and silicon-based laser. Having worked closely with Mario for many years, I’d like to share some of the history that led to this new achievement.

Before the turn of the millennium, silicon photonics remained an unlikely candidate for fiber optics. Silicon lacked many of the capabilities required for optical communication. Intel’s own Silicon Photonicsresearch has its roots in a debug tool developed by Mario in the late 1990s called the Laser Voltage Probe. The “LVP” became a standard tool to allow debug engineers to measure transistor signals on microprocessors by probing through the back side of the silicon with an infrared laser beam.

About a year or so later, Mario pitched an idea to Intel senior management for a silicon-based telecom optical switch, based on the same effect exploited by the LVP. After a few years of research it became apparent that the best use of this switching technology would be to create a fast modulator (an optical data encoder), which did not exist yet in silicon above a mere 20 MHz. The initial goal was ~1 GHz. Amid much skepticism, the team not only met the goal, they exceeded it. Today, silicon modulators at Intel Labs can send data at rates of 40 Gbps.

Mario’s vision included three phases of research and development: I) prove feasibility with demonstration of optical building blocks, then II) move to integration, and finally III) high volume manufacturability. For the middle part of the past decade, his team focused on phase I, developing a variety fundamental building blocks such as photodetectors, lasers, and modulators, and then scaling their performance to higher speeds.

Soon after, the team shifted focus from the development of building blocks to phase II: integration. The 50 Gbps silicon photonics link is the result of that effort, and required Mario’s team to put devices with different process recipes onto the same piece of silicon, assemble them on to circuit boards, and connect them to optical fibers to create an end-to-end link. Read more about the device here.

Using silicon allows one to benefit from the decades of high volume manufacturing infrastructure developed for silicon integrated circuits such as microprocessors. We’ve seen what silicon integration can do for electronics, and I believe we will get similar benefits from silicon photonics.

Mario is now leading the team into phase III: Tackling the remaining challenges that could stand in the way of high-volume production of these devices. This includes researching the issues of making reliable integrated devices economically on a large scale, as well as continuing to increase levels of integration, performance, and scalability. 50Gbps is just a beginning – Mario expects to see 1 Terabit/s coming out of a single silicon chip in the near future.

So, again, I congratulate Mario and his team for this well-earned award. He has helped to take silicon photonics from a technology that few believed in, to one we can now see approaching on the horizon for a variety of applications.

It is inspiring to see the enthusiasm and amazing work that these kids are bringing to their various fields of study.

]]> http://blogs.intel.com/intellabs/2011/03/28/future_lab_intel_science_talen/feed/ 1 http://blogs.intel.com/intellabs/2011/03/16/scc-green/ http://blogs.intel.com/intellabs/2011/03/16/scc-green/#comments Wed, 16 Mar 2011 08:00:00 +0000 http://blogs.intel.com/research/2011/03/16/scc-green/ Read more >]]> I’m happy to share today that the government of Germany has presented Intel with an award for the development of our 48-core concept vehicle, the Single Chip Cloud Computer. The research chip won a German Innovation Prize for Climate and the Environment in the category “Environmentally Friendly Technologies.” The German Federal Ministry for the Environment, Nature Conservation and Nuclear Safety and the Federation of German Industries presents these awards each year to acknowledge innovations that protect the climate and the environment. Franz Olbrich, from the lab in Germany which co-led the design of the SCC, traveled to Berlin to accept the award today on behalf of the company.

Developing ‘green IT’ is an essential focus for Intel researchers, and the fact that Intel is one of largest purchasers of renewable energy shows how important resource conservation and sustainability is for the company’s operations. Information technology now causes carbon emission comparable to that of civil aviation. At first a many-core processor might seem like an unlikely candidate to address these issues. Doesn’t more computation mean more energy spent?

The answer is: not if you spend that energy wisely. The SCC, along with our entire Tera-scale computing research program, exists as a part of a larger effort to do more with less, computationally. This is because breaking down processing tasks into more and more parallel elements, running on streamlined cores, is a more energy-efficient approach than making chips run at faster clock speeds. That is, provided that this parallel computing can be done effectively. The SCC prototypes a variety of research techniques to make this division of work more efficient so that the energy benefits of many-core can be more fully realized.

In addition to raw parallelism, the SCC incorporates fine-grain power management features that allow software applications to determine how much energy is needed at a given time and for a given task. Clock frequencies and voltages can be set to different levels across the chip depending on application needs. Cores or even entire banks of cores can sleep and wake as needed. The 48 cores require just 25 watts in idle mode or 125 watts when running at maximum performance, which is comparable to the consumption of two standard household light bulbs. Imagine applying this kind of capability across large systems such as data centers, and you can see how the power savings would multiply.

The SCC has also been shared with worldwide research partners through Intel’s recently launched Many-core Applications Research Community (MARC), a program aimed at spurring innovations in highly parallel software. More than 100 teams are conducting research on programming models, operating systems, development tools and programming languages for both microprocessors and data centers of the future.

As a final note – in accepting the award Franz also announced today that Intel plans to match the 25,000 Euro prize and donate it to a scholarship program which sponsors talented, high-profile students in Germany.

]]> http://blogs.intel.com/intellabs/2011/03/16/scc-green/feed/ 1 http://blogs.intel.com/intellabs/2011/03/01/future_lab_cloud_gaming/ http://blogs.intel.com/intellabs/2011/03/01/future_lab_cloud_gaming/#comments Tue, 01 Mar 2011 11:02:43 +0000 http://blogs.intel.com/research/2011/03/01/future_lab_cloud_gaming/ Read more >]]> Utilizing the resources of cloud based gaming opens up the possibility of even more advanced graphics that couldn’t be done on a single machine today. Researchers at Intel are working with university collaborators and game developers to explore real-time ray tracing to show new special effects for games. Notebooks, netbooks and tablets get access to playing high-end games. Find out more on this episode of Future Lab.

]]> http://blogs.intel.com/intellabs/2011/03/01/future_lab_cloud_gaming/feed/ 0 http://blogs.intel.com/intellabs/2011/02/23/ray_traced_games_in_the_cloud/ http://blogs.intel.com/intellabs/2011/02/23/ray_traced_games_in_the_cloud/#comments Wed, 23 Feb 2011 08:00:00 +0000 http://blogs.intel.com/research/2011/02/23/ray_traced_games_in_the_cloud/ Read more >]]> The rise of the cloud offers new opportunities for gaming. Through the ability to offload intensive calculations not only leightweight clients like notebooks, netbooks and tablets get access to playing high-end games, but it also opens the doors to even more advanced graphics that couldn’t be done on a single machine today. In the article at the Intel Software Network we describe a research demo that uses real-time ray tracing to show new special effects for games. The calculations are done in the cloud on Intel’s Many Integrated Core (MIC) archictectures. Head over and learn more!

We showed a demonstration of this research at the 2010 IDF

]]> http://blogs.intel.com/intellabs/2011/02/23/ray_traced_games_in_the_cloud/feed/ 0 http://blogs.intel.com/intellabs/2011/02/16/future_lab_health_care_for_sen/ http://blogs.intel.com/intellabs/2011/02/16/future_lab_health_care_for_sen/#comments Wed, 16 Feb 2011 14:38:58 +0000 http://blogs.intel.com/research/2011/02/16/future_lab_health_care_for_sen/ Read more >]]> Researchers around the world are searching for ways to help seniors remain healthier and live independently in their homes for longer. Intel is working on new sensing devices that can feed data to a central hub that infers whether a person is getting enough sleep, taking their meds on time and feeding themselves properly. The technology relies on improved broadband access. The Obama Administration just announced it’s spending $5 Billion over the next five years to extend broadband to 98% of Americans. In this week’s episode of Future Lab, Deirdre Kennedy interviews Terry O’Shea and Eric Dishman from Intel and also talks to Patricia Abbott from John Hopkins School of Nursing and Medicine.

]]> http://blogs.intel.com/intellabs/2011/02/16/future_lab_health_care_for_sen/feed/ 0 http://blogs.intel.com/intellabs/2011/02/01/opsis/ http://blogs.intel.com/intellabs/2011/02/01/opsis/#comments Tue, 01 Feb 2011 08:00:00 +0000 http://blogs.intel.com/research/2011/02/01/opsis/ Read more >]]> Today the University of Washington launched an exciting program that we hope will help trigger a new technology revolution around integrated silicon photonics chips. This program, which we call OpSIS (Optoelectronics Systems Integration in Silicon), will provide a silicon photonics wafer service to give researchers the ability to design and build experimental optical chips.

My team at Intel Labs has been researching silicon photonics devices for nearly a decade with a vision of creating silicon chips that can send trillions of bits per second across an optical fiber. After years of experimentation, I have come to believe that photonic integrated circuits will truly be a transformative technology, with a potential similar to the development of electronic integrated circuits and a diverse set of applications. Silicon ICs have, in only a few decades, been developed to address countless applications – they are used for computers, music amplifiers, sensors, radios, displays and many other devices. Likewise, silicon photonics will have impact to many other areas well beyond high-speed communications. These include sensing, wireless, and bio-medical devices.

With OpSIS, we are helping to develop the silicon photonics industry by reproducing a key factor in the success of the silicon IC. OpSIS is modeled in part after MOSIS (Metal Oxide Semiconductor Implementation Service), an IC wafer service for R&D started in 1981. MOSIS was (and still is) operated by the University of Southern California and assembles designs from multiple researchers on multi-project silicon wafers to share the cost of fabrication. OpSIS will do the same for silicon photonics chips. In fact, Carver Mead, the co-founder of MOSIS and coiner of the term “Moore’s Law” (among many other things) is speaking today along with Intel CTO Justin Rattnerin support of UW’s new optical wafer service.

OpSIS is the brainchild of UW professor Michael Hochberg, who will lead the program. Intel Labs has provided input and some funding to help launch this new service. The photonics technology lab here at Intel and I will also continue to help consult and provide assistance where possible to help OpSIS get operational. OpSIS has other significant partners. BAE Systems will provide fabrication facilities. The U.S. Air force is supporting Prof. Hochberg with funding to help OpSIS get started as well as for some special military interests in using silicon photonics for new radar technology. We have half a dozen researchers already signed up to hop on the first wafer fabrication service run.

As a final note – OpSIS will be important not just for innovation, but for education. In order to develop a new industry, we need to develop a new generation of engineers. OpSIS will provide university students with the ability to build their own silicon photonics experiments – a necessary capability that doesn’t exist today. These students of today will become the innovators and leaders of tomorrow that grow this nascent industry into one that touches people’s lives in ways we can’t even predict today. This is an exciting time for silicon photonics and the potential impact it will have to everyone’s lives.

]]> http://blogs.intel.com/intellabs/2011/01/31/future_lab_visual_computing_la/feed/ 0 http://blogs.intel.com/intellabs/2011/01/26/intel_science_technology_cente/ http://blogs.intel.com/intellabs/2011/01/26/intel_science_technology_cente/#comments Wed, 26 Jan 2011 09:00:00 +0000 http://blogs.intel.com/research/2011/01/26/intel_science_technology_cente/ Read more >]]> Today Intel Labs is embarking on a new and exciting way of engaging the U.S. academic community in long-term collaborative research. Our goals in establishing Intel Science and Technology Centers are to fund significant academic research in areas that are important to Intel’s long term future and to capture new ideas and fresh perspectives from the academic community and bring into Intel. Using this model, we hope to engage a large number of universities and leading academics in long term research in a way that brings together vibrant research communities that will advance the state of the art in technology areas of vital importance to Intel and the industry.

I’m especially excited about the prospect of investing with significantly large research grants in the leading U.S. universities. Through the ISTC model, Intel is increasing by as much as 5x the size of our direct investment in U.S. academic community over what we were investing through our previous Open Collaborative model. This is good for Intel, good for the universities, and especially good for promising young students and researchers who are considering whether or not to go on to graduate school. One of our aims is to really encourage, and provide the means by which, young up-and-coming researchers will go to graduate school and eventually decide on a long-term career at Intel.

The Visual Computing center being announced today is the first ISTC to be established, and we are actively working toward establishing centers with several of our university partners. We hope to launch half a dozen ISTCs by the end of 2012.

I am looking forward to the new opportunities these ISTCs will create, and we continue to invite dialog and discussion from across the company and the academic community in our efforts to drive Intel’s academic research programs.

EDITOR’S NOTE:

Thanks to everyone for their inquiries about the ISTC program. At present, the only publicly announced ISTC concerns visual computing. Other topics have been selected for 2011, but we are still putting in place the Intel leadership teams and giving them the time and space to work out their basic approach. When the time is ripe (weeks to months) they will reach out to the academic community in ways that make the most sense for the specific focus area.

Beyond this year, we are not prepared to commit to any specific process for selecting ISTC topic areas and schools. While there is not an open call for proposals, we are passing individual inquiries on to the ISTC management team. Having said that, since research at Intel is often driven in a grassroots fashion, the best thing to do is keep collaborating with Intel researchers to develop and communicate a vision that people get excited about.

]]> http://blogs.intel.com/intellabs/2011/01/26/intel_science_technology_cente/feed/ 7 http://blogs.intel.com/intellabs/2011/01/26/intel_launches_istc_on_visual/ http://blogs.intel.com/intellabs/2011/01/26/intel_launches_istc_on_visual/#comments Wed, 26 Jan 2011 09:00:00 +0000 http://blogs.intel.com/research/2011/01/26/intel_launches_istc_on_visual/ Read more >]]> We at Intel are really excited about the launch of the Intel Science and Technology Center for Visual Computing (ISTC-VC) which will bring together researchers from Stanford, Berkeley, Cornell, Princeton, Harvard, The University of Washington, UC Irvine and US Davis to work hand-in-hand with Intel researchers on Visual Computing. Given the dominance of the visual cortex amongst the sensory processing centers within the brain, visual computing will undoubtedly have a huge influence on future computing system design. This is borne out by the recent trend towards the integration of GPU architecture into main stream processors such as the 2nd Generation Intel Core i5 (Sandybrige) processors. The ISTC-VC researchers will focus on fundamental breakthroughs that will enable the broad adoption of visual computing technologies. The Center’s research will be organized into the following four themes:

Perceiving People and Places: The proliferation of digital cameras, coupled with explosive progress in computer vision, has led to major breakthroughs in sensing technologies. We now use these technologies in our everyday lives—in cameras, maps, and search—with many more uses on the way (cars, personal robotics, smart homes, etc.). These advances are due in large part to the recent development of extremely accurate and robust low-level computer vision algorithms for feature detection, matching, and 3D measurement. The next wave of breakthroughs will be defined by the ability to infer high-level functional and semantic information about people and environments from images and video. Beyond telling you if a person is present, next generation systems will reliably perceive who it is and what that person is doing, down to the level of actions and activities. Such capabilities will be transformational across a wide spectrum of applications—using your body to replace the mouse (as in Microsoft?s upcoming Kinect/ Project Natal game console) is just the tip of the iceberg. Similarly, next generation 3D vision systems will go beyond raw depth measurement, to also perceive the functional and semantic content of the scene. While current 3D modeling methods represent the scene as an unorganized mass of points or triangles, next generation systems will recognize what is in the scene—doors, chairs, stairs, sidewalks, windows, tables, and other components. Beyond scene visualization, these new capabilities will enable applications such as home remodeling pre-visualization and building searchable, functional 3D city models from online imagery and LIDAR data that you can interact with in an online virtual world.

Content Creation: Creating visual content is difficult. Consider any visual medium: photographs, video, 3D models, diagrams and illustrations, realistic 3D renderings, animation, slide presentations, webpage design, games, etc. The software tools for creating such visual media usually include sophisticated interfaces that provide precise and flexible control over the content. Yet, they are dauntingly difficult to learn to use effectively. Although cameras now allow anyone to easily capture photos and video, tools for manipulating such media and creating other forms of visual content remain accessible only to experts. We believe that two recent trends offer the promise of enabling a significantly wider set of everyday users (of all skill levels) to produce visual content:

1. Collaboration Via the Internet: The World Wide Web allows people to work together and leverage complimentary skills to collaboratively create content. Already content sharing sites like Flickr and YouTube allow people to add photos and video to their Visual projects. Crowd sourcing frameworks (e.g. Amazon Mechanical Turk, CrowdFlower etc.) allow requestors to post content creation tasks and that other workers can fulfill for small payments. Multi–?player games provide other types of incentives to create content. We believe that such collaboration will fundamentally change the way people create visual content.

2. New Sensing Hardware for Input: Mobile devices have recently made video cameras, microphones, and multi-touch screens commonplace. Similarly gaming systems are poised to make 3D cameras and accelerometers similarly cheap and ubiquitous. Such sensors enable simple, direct, gestural Interaction and can provide greater recognition of context. We believe that developing content creation interfaces that take advantage of such hardware will increase accessibility of these tools to and much wider set of users.

Communication is fundamental to human existence. It is clear that we can communicate at far greater data rates using visual content vs. language, i.e., a picture tells a thousand words. The current difficulty of creating visual content limits our ability to express ourselves visually. Simplifying content creation will enable the effortless creation of sophisticated visual content such as animations and videos, enabling us to express information and ideas at a much higher comprehension rate than you could using the spoken or written word, especially across cultural and/or language divides. Great communicators use language to effectively communicate visions. If we could all create such visions on our computers, we would all become great communicators.

Scalable Real-Time Simulation: The simulation of physical phenomena is central to visual computing: from light transport and appearance, to the dynamics of fluids and solids, the movement of virtual characters, and increasingly the sounds these systems make. Such multi-sensory simulations are notoriously expensive to compute making it difficult to realize real-time simulations and develop simulation applications for mobile computing. This theme will address physics-based simulation and multi-sensory rendering in an integrated and connected manner: light, motion and sound. Research will be focused on the unique challenges posed by simulated virtual characters. In addition, this theme will explore the computational challenges of scalable simulation as it relates to multi-physics and multi-sensory software integration, parallel and distributed computing, interactive and hard real-time computation, model complexity, e.g., planetary-scale simulation, the spectrum of computing platforms (from mobile to the cloud), and ever-present memory and bandwidth concerns.

Graphics and Systems: To create the future architectures needed to support advances such as those outlined in the above three themes, ISTC-VC researchers will explore next generation architectures and tools that address the following four crucial technology trends:

1. Personal computing is increasingly moving away from traditional desktop computers toward mobile devices, ranging from laptops to tablets to pocket-sized computers, phones, and other battery-powered devices. The result is a need to design systems that focus on mobility with an emphasis on power-aware design, miniaturization, and efficient computing given a minimal cost, power, and volume budget.

2. Just as computing is moving away from traditional PCs onto mobile devices, computing is also moving in the opposite direction, into the cloud, which can deliver superior reliability, cost, and scalability than the desktop.

3. GPU design has historically incorporated both fixed-function and programmable parts. While a recent trend toward more flexibility has increased the focus on programmable components, the superior power efficiency of fixed-function components merits their continued study. The likely result is heterogeneous graphics systems with heterogeneity at many levels: fine-grained (such as integer vs. floating point ALUs); medium-grained (such as rasterization or texture filtering units); and coarse-grained (CPU cores vs. GPU cores). Determining the right mix of units, and programming the resulting heterogeneous systems, is one of the grand systems design challenges in computing.

4. Finally, at all levels of computing from mobile to desktop to the cloud, we see a growing gap between the capabilities of the hardware–what the system could do–and the delivered performance of the Software–what the system actually does. As the hardware becomes more complex, more parallel, and more heterogeneous, we see a real and growing need for solving the programmability problem by building software that allows programmers and users to make the most of the hardware. These trends will affect designs, implementations, and software support for future graphics systems of all sizes, from small, inexpensive mobile systems to traditional single-node GPUs to visual computing in the cloud.

]]> http://blogs.intel.com/intellabs/2011/01/26/intel_launches_istc_on_visual/feed/ 0 http://blogs.intel.com/intellabs/2011/01/18/future_lab_sleep_science/ http://blogs.intel.com/intellabs/2011/01/18/future_lab_sleep_science/#comments Tue, 18 Jan 2011 16:47:48 +0000 http://blogs.intel.com/research/2011/01/18/future_lab_sleep_science/ Can’t seem to a good night’s sleep? Think counting sheep is the only solution? Listen to this week’s Future Lab episode to find out how technology could help you get better rest.

]]> http://blogs.intel.com/intellabs/2011/01/18/future_lab_sleep_science/feed/ 0 http://blogs.intel.com/intellabs/2011/01/12/future_lab_connected_home/ http://blogs.intel.com/intellabs/2011/01/12/future_lab_connected_home/#comments Wed, 12 Jan 2011 08:39:33 +0000 http://blogs.intel.com/research/2011/01/12/future_lab_connected_home/ Read more >]]> Your refrigerator can tell you if the door is ajar, your blu-ray player connects to Netflix, your car can be started remotely – but how can all these various devices and systems work together? With diverse platforms and network configurations, as well as manufacturers’ unique characteristics built into computing gear, audio and video equipment and appliances, the task of getting them to work together usually requires more than getting the settings correct under a PC’s preferences menu. Intel researchers and industry partners are exploring ways to make connecting all your devices as easy as turning on the radio.

]]> http://blogs.intel.com/intellabs/2011/01/12/future_lab_connected_home/feed/ 0 http://blogs.intel.com/intellabs/2010/12/15/future_lab_the_future_of_tv/ http://blogs.intel.com/intellabs/2010/12/15/future_lab_the_future_of_tv/#comments Wed, 15 Dec 2010 13:59:43 +0000 http://blogs.intel.com/research/2010/12/15/future_lab_the_future_of_tv/ Read more >]]> What happens when television technology merges with the computer, when your devices know who you are, what you like to watch, and how? What transformations can we expect in the business of TV?

Find out what leading researchers and scientists see for the future of television and how it might impact our lives, in this week’s episode of Future Lab Radio.

]]> http://blogs.intel.com/intellabs/2010/12/15/future_lab_the_future_of_tv/feed/ 0 http://blogs.intel.com/intellabs/2010/12/06/future_lab_better_photos/ http://blogs.intel.com/intellabs/2010/12/06/future_lab_better_photos/#comments Mon, 06 Dec 2010 09:58:43 +0000 http://blogs.intel.com/research/2010/12/06/future_lab_better_photos/ Read more >]]> As an ametuer photographer, I am always trying to improve the aesthetic qualities of my pictures. Taking better photos isn’t always about having the most expensive equipment, it’s about using the tools you have to their fullest potential. But despite my best efforts, more often than not, I end up trying to fix my compostion in post-production. Researchers at Intel are exploring ways that technology can enhance the aesthetic quality of digital photographs thru spatial recomposition.

Find out more about this research in the latest episode of the Future Lab podcast series.

]]> http://blogs.intel.com/intellabs/2010/12/06/future_lab_better_photos/feed/ 0 http://blogs.intel.com/intellabs/2010/11/30/future_lab_protecting_privacy/ http://blogs.intel.com/intellabs/2010/11/30/future_lab_protecting_privacy/#comments Tue, 30 Nov 2010 15:27:21 +0000 http://blogs.intel.com/research/2010/11/30/future_lab_protecting_privacy/ Read more >]]> Intel Labs is investigating technologies to protect people from privacy and security risks of everyday sensing systems. As advances in technology accelerate, context-aware sensing systems are increasingly being integrated into everyday life. Although the added benefit of context-aware systems is often clear (e.g., entertainment, home security, encouraging sustainable behaviors, etc.), Intel is focusing on helping people understand and control how their data is collected and used.

In this Future Lab podcast, researchers discuss some of these tools as well as concepts that can help mitigate the unauthorized use of private information.

]]> http://blogs.intel.com/intellabs/2010/11/30/future_lab_protecting_privacy/feed/ 0 http://blogs.intel.com/intellabs/2010/11/16/enhancing_everyday_experiences/ http://blogs.intel.com/intellabs/2010/11/16/enhancing_everyday_experiences/#comments Tue, 16 Nov 2010 15:12:24 +0000 http://blogs.intel.com/research/2010/11/16/enhancing_everyday_experiences/ Read more >]]> Technology comes in all shapes and sizes these days. We have smart phones, smart remotes, smart cameras – but what are some of the ways these devices can make our lives easier, safer, and more fun? Researchers at Intel’s lab in Seattle are exploring ways that sensors and smart devices can change the way we work, play and live. At the recent lab open house, many of these projects were on display: From a TV remote that can recognize who is using it, to a robot that plays chess, to fire breathing lego dragons.

Many of the research projects used 3D cameras to provide an enhanced experience, whether it was playing games, making dinner or exploring the world around us. A robot played chess with people who were brave enough to match wits, patiently waiting its turn, delicately moving up a pawn or capturing a knight.

Playing legos gets another level of fun with real-time computer vision, 3D cameras, micro-projections and gesture recognition and object tracking….not to mention being really cool!!

Researchers are also exploring ways sensors can be used to enhance our daily activities. For example, a TV remote with a simple sensor uses machine learning to recognize who is holding it, and can work with a smart TV to create a personalized user experience.

]]> http://blogs.intel.com/intellabs/2010/11/16/enhancing_everyday_experiences/feed/ 0 http://blogs.intel.com/intellabs/2010/10/25/future_lab_measuring_vineyard/ http://blogs.intel.com/intellabs/2010/10/25/future_lab_measuring_vineyard/#comments Mon, 25 Oct 2010 15:18:21 +0000 http://blogs.intel.com/research/2010/10/25/future_lab_measuring_vineyard/ Read more >]]> There are numerous practical applications for computer vision but typically the cost of gathering the data has been time consuming and expensive. Researchers at Intel Labs and Carnegie Mellon University in Pittsburgh are looking at low cost, reliable ways that computers can help farmers manage and track their crop yield. Deploying low cost sensors in a vineyard and using off the shelf cameras, they are building computer models that can distinguish grapes hidden among leaves and shadows.

Check out the latest Future Lab podcast to find out more about this research project.

]]> http://blogs.intel.com/intellabs/2010/10/25/future_lab_measuring_vineyard/feed/ 2 http://blogs.intel.com/intellabs/2010/10/11/future_lab_mapping_the_network/ http://blogs.intel.com/intellabs/2010/10/11/future_lab_mapping_the_network/#comments Mon, 11 Oct 2010 10:45:15 +0000 http://blogs.intel.com/research/2010/10/11/future_lab_mapping_the_network/ Read more >]]> Brain trauma affects more than 2 million people in the U.S. each year because of accidents and participation in sports. But little is understood about the connections within the brain that can be broken but not detected. Using MRI scans, computer scientists are helping brain researchers to map the network of tracts-containing hundreds of thousands of axons-in the human brain. This research is very exploratory but promises to yield new discoveries about the brain. Researchers from the University of Pittsburgh and Intel are exploring ways that computer vision could help surgeons diagnose and operate on brain injuries with precision and accuracy.

]]> http://blogs.intel.com/intellabs/2010/10/11/future_lab_mapping_the_network/feed/ 1 http://blogs.intel.com/intellabs/2010/10/08/alexandra_lyaplina/ http://blogs.intel.com/intellabs/2010/10/08/alexandra_lyaplina/#comments Fri, 08 Oct 2010 07:45:00 +0000 http://blogs.intel.com/research/2010/10/08/alexandra_lyaplina/ Read more >]]> Alexandra Lyaplina holds a Masters degree in Economics and a Bachelors degree in International Relations. Alexandra has worked at various capacities within the Public Sector and Information & Communication Technology (ICT) industry, and has been with Intel Corporation for the past 3,5 years.

]]> http://blogs.intel.com/intellabs/2010/10/08/alexandra_lyaplina/feed/ 0 http://blogs.intel.com/intellabs/2010/10/08/alexandra_lyaplina_holds_a_mas/ http://blogs.intel.com/intellabs/2010/10/08/alexandra_lyaplina_holds_a_mas/#comments Fri, 08 Oct 2010 07:15:02 +0000 http://blogs.intel.com/research/2010/10/08/alexandra_lyaplina_holds_a_mas/ Read more >]]> Alexandra Lyaplina holds a Masters degree in Economics and a Bachelors degree in International Relations. Alexandra has worked at various capacities within the Public Sector and Information & Communication Technology (ICT) industry, and has been with Intel Corporation for the past 3,5 years.

]]> http://blogs.intel.com/intellabs/2010/10/08/alexandra_lyaplina_holds_a_mas/feed/ 0 http://blogs.intel.com/intellabs/2010/10/08/intel_at_the_heart_of_european/ http://blogs.intel.com/intellabs/2010/10/08/intel_at_the_heart_of_european/#comments Fri, 08 Oct 2010 05:36:21 +0000 http://blogs.intel.com/research/2010/10/08/intel_at_the_heart_of_european/ Read more >]]> Last week we participated in ICT 2010: Shaping the European Research and Innovation Agenda for the Next Decade, the biggest research conference for information and communication technologies organized by the European Commission’s Directorate General for the Information Society and Media. The conference was held in Brussels and gathered more than 6000 experts in all the fields of ICT research, policy and industry. More than 200 projects representing all the possible ICT fields of research were presented at the exhibition.

First of all, on behalf of Intel Labs Europe (ILE), we are happy to congratulate the winners of the ICT 2010 Best Exhibit Awards namely: VECTOR project from the Digital Society Zone, investigating and developing a miniaturized robotic pill for advanced diagnostics and therapy in the human digestive tract with the aim to make a significant contribution to the diagnosis and treatment of digestive cancers and their precursors (1st Prize Exhibition), SOA4All project from the ICT Connects Zone, creating a framework for integrating technical advances into a domain-independent service delivery platform (2nd Prize Exhibition) and Saferider project from the Safety and Security Zone, driving the advanced telematics for enhancing the safety and comfort of motorcycle riders, aiming to improve rider safety (3rd Prize Exhibition). These projects got the majority of votes from ICT 2010 participants, and were awarded during the Closing Plenary by the Minister for Economy and Simplification of Belgium Vincent Van Quickenborne, the Deputy Director General, Information Society and Media Anti Peltomäki and Prof. Martin Curley, Director of ILE. Since ILE is committed to accelerating digital transformations and fostering European innovation and research, we were delighted to support the Best Exhibit Prize, and would like to sincerely thank the event organizers. As Prof. Curley said: “It’s not just about exhibit excellence, but about the diffusion and dissemination excellence”.

We also participated in the conference itself, which this year was focused on two key themes: ICT for sustainable growth in a low carbon economy, and ICT in the daily life of citizens and the importance of public participation in the innovation process. The conference was opened with a plenary debate on “Research and Innovation in the Digital Agenda for Europe” where European policymakers and CEOs of ICT companies shared their vision of the Europe’s ICT research and innovation policy for the next decade. The key outcome of the discussion was the acceptance of the fact that some profound changes are taking place in the economy and society, and that the whole ICT industry will need to shape itself.

This discussion continued on the following day, and another important message: The future is going to be about services, and there is a huge potential for the industry, but the stakeholders will need to change the way of thinking. Intel Labs Europe, being member of the Open Innovation Services and Policy Group (OISPG) and other network organizations is participating actively in the process of shaping the European services sector, and will continue its efforts towards raising its competitiveness.

On the second day Martin Curley delivered a talk at the Panel “Digital Roadmap to the Future” devoted to major transformative trends in ICT and the next scientific breakthroughs that will shape future technological developments and application scenarios for 2030 and beyond. In his talk he outlined how new products and emerging technologies being developed by Intel will help fuel a sustainable future, and discussed the synthesis of three mega trends coming together. These are the increasing acceleration of digital transformations, the ever-growing awareness of the need for sustainable paradigms and solutions, and the increasing importance of mass collaboration. For the letter, he cited as an example the Innovation Value Institute, a member of the Intel Labs Europe Network with 50 public and private sector organizations partnering together to research, develop and diffuse new models and methods for IT management and IT Innovation.

Participation in the EU’s 7 Framework Programme (FP7), led by the European Commission’s Directorate General for Research, is one of the key aspects of ILE activities. More and more Intel labs across Europe are joining this unique program to help reach the goals of growth, competitiveness and employment in the European Union. To date, we are partnering on more than 20 projects with over 200 European organizations across 6 R&D labs, and the number is growing. Two of these were presented at the ICT 2010 exhibition.

Representatives of our SLA@SOI project, an Integrated Project (IP) researching the systematic management of service-oriented infrastructures on the basis of formally specified service level agreements (SLAs), organized an Information Day “Research/Industry Collaboration on Open Source Cloud Middleware” during the Conference with a goal to help users, engineers and researchers in cloud deployments to identify better ways to collaborate on developing European open-source technology. The session also discussed future directions and required research activities to position cloud as an ideal substrate for service delivery in the future internet.

PERSIST: Personal Self-Improving Smart Spaces was another example of our participation in the FP7 initiatives, shown in the Safety and Security Zone. The vision of PERSIST is of a Personal Smart Space (PSS), which is associated with the portable devices carried by the user and which moves around with him/her, providing context-aware pervasiveness to the user at all times and places. The project’s objective is to develop Personal Smart Spaces that provide a minimum set of functionalities which can be extended and enhanced as users encounter other smart spaces during their everyday activities. The demo focused on 4 key scenarios: a reconfigurable room, a personalized smart workspace, a learned behavior scenario, and an African aid negotiation scenario. Visitors were able to interact with the demonstrators and to experience PSS features such as proactive service control, context sharing and group preference conflict resolution, and trust-based privacy negotiation.

]]> http://blogs.intel.com/intellabs/2010/10/08/intel_at_the_heart_of_european/feed/ 2 http://blogs.intel.com/intellabs/2010/10/05/future_lab_cloud_computing/ http://blogs.intel.com/intellabs/2010/10/05/future_lab_cloud_computing/#comments Tue, 05 Oct 2010 08:00:37 +0000 http://blogs.intel.com/research/2010/10/05/future_lab_cloud_computing/ Read more >]]> Open Cirrus is an open cloud-computing research testbed designed to support research into the design, provisioning, and management of services at a global, multi-datacenter scale. An Internet service such as Facebook is one example of cloud computing which presents certain data management challenges. Large sets of data that enterprises seek to move to the cloud present significant challenges. However the benefits, which include cost-savings, scalability and automation promise to be substantial.

Check out the latest installment of Future Lab Radio to find out what Intel, Yahoo, HP and university researchers are working on in “the cloud”.

]]> http://blogs.intel.com/intellabs/2010/10/05/future_lab_cloud_computing/feed/ 0 http://blogs.intel.com/intellabs/2010/10/01/what_do_robots_stem_cells_and/ http://blogs.intel.com/intellabs/2010/10/01/what_do_robots_stem_cells_and/#comments Fri, 01 Oct 2010 16:06:38 +0000 http://blogs.intel.com/research/2010/10/01/what_do_robots_stem_cells_and/ Read more >]]> Ever wondered what it would take to make a robot that can avoid obstacles? How can computers make you a better photographer? What can technology do to improve stem cell research? These are just some of the projects going on at Intel Labs Pittsburgh.

I recently attended the lab open house. This annual event is an opportunity to experience the full range of research activities and collaborations, via posters, demonstrations, and direct conversation with the researchers and students involved. On display were the latest work with Carnegie Mellon, University of Pittsburgh, and many others. Research projects covered topics from personal mobile robots, computer-assisted medicine, parallel machine learning, power efficient server design, cloud computing on big data, cache-savvy algorithms, using solid-state disks for databases, multicore system design, and optical interconnects for datacenters.

Collaborative Robotics

Researchers from Intel and Carnegie Mellon University want to make robots common in people’s everyday lives by increasing their usefulness and acceptance. They acknowledge the current limitations of robot autonomy and explore methods for effective human-robot collaboration. There goal is simple – robots helping people & people helping robots.

To accomplish the goal of operating cooperatively with people, robots need to overcome a new set of challenges, in addition to the standard difficulties of perception, planning, navigation & manipulation. High among these are ‘people skills’ – detecting, recognizing and understanding the actions of humans in the environment. We are investigating opportunities for collaboration when the human and robot are near each other (local collaboration) and when they are far apart (remote collaboration). We are developing a rich and modular set of robot skills common to multiple applications. Such skills enable robots to provide new compelling services.

Better Photography thru computation

We all take lots of photos, but they don’t always turn out that great. Wouldn’t it be nice if there was a way to have your computer help you become a better photographer? This project using machine learning, spatial recompostion, traditional photographic aesthetics (Rule of 3rds and Fibonacci’s Rule) combined with minimal user interaction to improve photos by 73%.

Stem Cell Tracking using Computer Vision

In the past, biologists have had to manually track stem cell proliferation but now by using computer vision algorithms, they are able to achieve the same accuracy levels using computers. This project was also displayed on a remote screen using the Open Cirrus cloud computing testbed. Being able to check on a project remotely will remove time constraints and enable biologists from around the world to utilize these tools for their experiments.

]]> http://blogs.intel.com/intellabs/2010/10/01/what_do_robots_stem_cells_and/feed/ 0 http://blogs.intel.com/intellabs/2010/09/27/future_lab_sens/ http://blogs.intel.com/intellabs/2010/09/27/future_lab_sens/#comments Mon, 27 Sep 2010 07:36:21 +0000 http://blogs.intel.com/research/2010/09/27/future_lab_sens/ Read more >]]> How can computer vision and machine learning help make your day to day life more enjoyable and provide valuable information that can improve decision making abilities? Socially Enabled Services (SENS) is a research project in this area that looks as how mobile devices can anticipate user needs. Find out more in this week’s Future Lab show.

]]> http://blogs.intel.com/intellabs/2010/09/27/future_lab_sens/feed/ 0 http://blogs.intel.com/intellabs/2010/09/26/ocstem/ http://blogs.intel.com/intellabs/2010/09/26/ocstem/#comments Sun, 26 Sep 2010 20:55:00 +0000 http://blogs.intel.com/research/2010/09/26/ocstem/ Read more >]]> Today, Intel, HP, and Yahoo! publically announced an expansion of our joint effort to accelerate innovation in the area of cloud computing, called “Open Cirrus.” We are very excited that four new members have joined this collaboration, and I think this provides a good opportunity to step back and understand why we at Intel Labs are investing in the project, and how this cloud research could impact people in the future.

Open Cirrus is, in essence, a giant tool to facilitate research. Each member provides a cluster of at least 1000 microprocessor cores, which are in turn networked to each other to form a worldwide cloud. Because of its open nature, this global testbed allows us to collectively research system and software innovations that make clouds work better. It also allows us to start working through a variety of issues related to operating clouds, running cloud applications, and sharing data over international boundaries. But, perhaps the most interesting part is that Open Cirrus allows us to provide a massive computing resource to researchers in a diverse array of fields.

I would like to highlight one such project that we briefly mentioned in the press release today, a collaboration between Intel and Carnegie Mellon Univerisity that could facilitate new developments in tissue engineering, regenerative medicine, and drug discovery. In turn, this could help lead to advancements in the ability to re-grow injured limbs or other body parts. It involves combining stem cell research, computer vision, and the computational power provided by Open Cirrus.

This research involves what are called “somatic stem cells” taken from adults. All adults have stem cells – they have been found in bone marrow, skin, skeletal muscles, teeth and several other tissues. Their function in the body is to maintain and heal the tissues in which they are found. However, the amount of stems cells found in adults is small, which leads to the need to find manufacturing processes to turn a few cells into large cultures sufficient for research and medical use.

An important concept associated with stem cells is what is called “stemness,” which essentially means the ability for a given cell to consistently differentiate, or transform, into other cells. The trick is to control how this transformation happens. An important factor that scientists use to achieve this control is the application of hormones, chemicals that can influence cell behavior.

But understanding how various hormones and other growth factors trigger what kind of behaviors in different candidate cells can be extremely labor intensive. Carnegie Mellon University has a process where they “print” a pattern of hormones that interact with different cells. Until recently, monitoring the growth behaviors of the various cells was a manual process, requiring hundreds of man hours to analyze the effects of just one pattern. Listen to our Future Lab Radio podcast on this topic to learn more.

This is where Open Cirrus comes into play. Working with Mei Chen from Intel Labs Pittsburgh, the researchers are using microscope-mounted cameras and time-lapse photography to monitor the cell growth instead of human eyes. The challenge is that accurately monitoring and tracking individual cells as they quickly develop in a large, constantly shifting population requires both cutting edge algorithms and a large amount of computation. The Open Cirrus testbed at Intel Labs Pittsburgh provides such a platform for massive cloud based computation, distributing the captured images to many processors to be analyzed in parallel.

This does two things: first, the computer can watch the cells continuously, potentially tracking much more information than a human could. For instance, a single cell in a large population can be tracked over a long period of time. As cells divide, the software can track their genealogy so that researchers can know which cells are siblings, cousins, or great-great-grandchildren of each other. In short, this gives the scientists much more detailed information about what happened with the cells. You can see the results in this short video clip. On the left, you’ll see the tagged cells. On the right you can see a graph of the cells’ positisons over time (the vertical axis).

The second benefit is that the scientists can dedicate more time to deriving meaning from these results rather than spending much of their time manually capturing them. Furthermore, it is a scalable solution – one could significantly increase the number of samples studied without having to bear the cost of hiring more researchers to monitor them.

I’d like to wrap up with a comment from Prof. Takeo Kanade, who is leading the research from the university side. According to him, the ability to precisely track thousands or millions of cells in real-time will open the door for even broader applications. In an email about the project, he emphasized that “executing it on the Open Cirrus cloud computing testbed has enabled us to realize a new usage model of computer vision that can make critical impact on the biological sciences.”

In the end, this is what Open Cirrus is about — not just creating a better cloud system, but catalyzing innovation across a wide variety of fields by proving a fundamentally better way to capture and analyze a wealth of data.

]]> http://blogs.intel.com/intellabs/2010/09/26/ocstem/feed/ 0 http://blogs.intel.com/intellabs/2010/09/24/congratulations_to_the_2010_in/ http://blogs.intel.com/intellabs/2010/09/24/congratulations_to_the_2010_in/#comments Fri, 24 Sep 2010 11:18:33 +0000 http://blogs.intel.com/research/2010/09/24/congratulations_to_the_2010_in/ Read more >]]> Intel PhD Fellowship Program winners announced!

As part of the ongoing commitment in supporting research at Universities, Intel has contributed over $1M to support top PhD students across the nation for 1 year of their research. The Intel PhD Fellowship Program is a very competitive process where students must first be pre-selected by their universities to be able to apply for the fellowship. Each selected student submits a thorough application which is reviewed by Intel Fellows and senior technologists who choose the winners. This is a very prestigious award, and winning students are all leaders in their field and come very highly recommended by their university and/or industry partners.

The fellowship program was started in the early 90′s by Gordon Moore to recognize and honor top students for their leading edge research in areas that would benefit the mankind; it was open to all fields of research. Gordon wanted to give back to those universities and communities who excelled at producing the top students. It was a way to build long lasting relationships with these universities, the professors and help create the next generation of technology leaders. The program has been supported every year for nearly 2 decades. Today’s program keeps that focus and also places an emphasis on developing students who are well aware of issues facing the Semiconductor, High Tech/IT fields. Every winning student is assigned a technical mentor in Intel who is also a leader in their field. Students are encouraged to work through their mentor and develop a deep, understanding of the technical issues facing the industry and be on the forefront of solving the technical challenges that lie ahead.

This year, 27 fellowships were awarded. All of the winning students were invited to Intel in Oregon the PhD Fellowship forum. During this forum, the students were able to meet and hear lectures from top technical leaders across the company including Ian Young, Kelin Kuhn, Genevieve Bell, Krishnamurthy Soumyanath and many others. They also attended a networking dinner with many of the speakers as well as other Intel Fellows and Senior Principal Engineers. The slideshow below highlights the forum. Without further adieu, here is the list of this year’s winners – Congratulations to each one of you!!!

]]> http://blogs.intel.com/intellabs/2010/09/24/congratulations_to_the_2010_in/feed/ 0 http://blogs.intel.com/intellabs/2010/09/22/the_exa-scale_supercomputer_of/ http://blogs.intel.com/intellabs/2010/09/22/the_exa-scale_supercomputer_of/#comments Wed, 22 Sep 2010 17:23:28 +0000 http://blogs.intel.com/research/2010/09/22/the_exa-scale_supercomputer_of/ Read more >]]> In the past year, Intel has launched three new research centers focused on different aspects of the same challenge: developing supercomputers with Exa-scale performance levels. That means a billion billion computations per second. To put that in context, if you had all ~6.9 billion people on earth scribbling out math problems at a rate of one per second, it would still take over four and a half years to calculate what an Exa-scale supercomputer could do in a single second. Exa-scale was the hot topic this week at the Intel European Research and Innovation Conference, and according to Prof. Thomas Lippert, director of the Jülich Supercomputing Center in Germany, these massive systems could arrive by the end of this decade.

Intel Sr. Fellow Steve Pawlowski, head of Central Architecture and Planning, predicted that demand for high performance computing will continue to rise, driven by computationally intensive tasks such as analyzing the human genome and the creation of climate models that can accurately predict weather patterns. But he emphasized that Exa-scale levels of performance can’t be achieved with today’s techniques, so new technologies must be developed. Pawlowski identified several major challenges facing Exa-scale researchers: energy-efficiency, parallelization, reliability, memory, storage capacity and bandwidth. Moreover, he said that it is important that hardware and software be woven together with a unified programming model.

Meeting these challenges will require a modular, cluster-based design that is both scalable and resilient, according to Prof. Lippert. He noted that the JUROPA supercomputer at his center in Jülich, currently the14th fastest computer in the world, consists of a cluster of about 15,000 processor cores. He predicted that a future exa-scale systems could be comprised of as many as 10 million cores – a major challenge in terms of power consumption and data communication amongst all the cores.

To achieve all of this, Intel has invested in collaborations with institutions that specialize in high performance computing. Three Intel labs, all members of the Intel Labs Europe network, now exclusively focus on Exa-scale computing research. These include the EXACluster Laboratory in Jülich, Germany (which collaborates closely with Prof. Lippert’s center), the Exascale Computing Research Center in Paris, France and the ExaScience Lab in Leuven, Belgium.

At the same time, researchers are hard work developing technologies for the future many-core microprocessors that will one day be at the heart of these clusters. For more on that – see my blog earlier this week on the Many-core Applications Research Community.

]]> http://blogs.intel.com/intellabs/2010/09/22/the_exa-scale_supercomputer_of/feed/ 0 http://blogs.intel.com/intellabs/2010/09/20/marc-scc/ http://blogs.intel.com/intellabs/2010/09/20/marc-scc/#comments Mon, 20 Sep 2010 12:56:09 +0000 http://blogs.intel.com/research/2010/09/20/marc-scc/ Read more >]]> I wanted to give an important update related to our research on future microprocessor architectures, particularly the “many-core” processors envisioned by our Tera-scale Computing Research Program. Last December, Intel Labs demonstrated the latest concept vehicle to emerge from this program, the 48-core Single-chip Cloud Computer. At the time, our CTO Justin Rattner also announced that we would make this experimental chip available to dozens of researchers worldwide, and even highlighted an early example collaboration via a demo presented by our friends at Microsoft Research.

Since then we have been working hard to make good on this commitment, soliciting and reviewing over 200 research proposals from academic and industry researchers around the globe, engineering a development platform suitable for external distribution, and even building a small ‘datacenter’ of a few dozen systems that can be accessed remotely – a cloud-based option for research on an architecture that itself was designed as a microcosm of a cloud datacenter.

To this end, today at the celebration of the 10th anniversary of the Intel R&D site in Braunschweig, Germany (whose researchers co-developed the SCC), we officially unveiled the Many-core Applications Research Community, or MARC for short. Under the new MARC program, the academic and industry researchers whose proposals were accepted will be able to use the SCC as a platform for next-generation software research. MARC will provide them with a new tool to solve challenges in parallel programming and application development that, hopefully, will in turn lead to dramatic new computing experiences for people and business in the future.

As of today, MARC consists of 51 research projects from 38 institutions worldwide. Aside from Microsoft Research, a few examples are the Karlsruhe Institute for Technology (KIT), the Technical University of Braunschweig, the University of Oxford, ETH Zurich, the Barcelona Supercomputing Center, the University of Edinburgh, the University of Texas, Purdue University, and the University of California San Diego. There are too many to list here, and there are also several other institutions whose proposals were accepted but who are still in the process of joining MARC (including some from both the eastern and southern hemispheres on the globe).

Although MARC has been launched with an initial focus on the SCC concept vehicle, we hope that the community itself proves to be as valuable as the chip. As such, we will explore sharing other hardware and software research platforms over time. For today, we’re excited to be providing some great minds around the world with a new research tool and a means to share their thoughts, ideas, and results with each other.

This research is part of an overarching effort to continue scaling processor capabilities while keeping power consumption low. With a wealth of data quickly accumulating across the internet, from tiny tweets to high-res video feeds, from customer data warehouses to medical imaging repositories — we will need these powerful parallel processors to sort and analyse this data flood in real time. Concepts like the SCC represent a promise of more intelligent technology for the future, and devices that reach out into the cloud to access computing resources which can automate our routine tasks and find us the information we need, perhaps before we even ask for it.

]]> http://blogs.intel.com/intellabs/2010/09/20/marc-scc/feed/ 0 http://blogs.intel.com/intellabs/2010/09/16/justin_rattner_aims_to_change/ http://blogs.intel.com/intellabs/2010/09/16/justin_rattner_aims_to_change/#comments Thu, 16 Sep 2010 08:42:48 +0000 http://blogs.intel.com/research/2010/09/16/justin_rattner_aims_to_change/ Read more >]]>

Justin Rattner, Intel CTO and director, Intel Labs, presented a compelling vision of the future in his IDF 2010 keynote yesterday entitled, Context: How it Will Really Change Everything. Justin outlined how context will be used to capture information about our daily lives which will enable our mobile devices to become true personal assistants. Context will enable technology to offer travel choices based on preferences entered or detected, track elderly people in order to predict or detect falls, or in fact ensure that we don’t accidentally send a picture to our boss of the sporting event we are attending when we are supposed to be working.

The concept of context-aware computing has been stirring in the research community for decades. Justin acknowledged the late Mark Weiser of Xerox PARC who articulated the original vision back in 1991. As technology has advanced since then, the potential for truly context aware computing is now able to become a reality.

According to Justin, context is everything and that makes it complex. If we get it right, it will propel an entire new set of experiences.

For a copy of Justin’s presentation and to review his keynote, visit the IDF Press Kit on the Intel Press Room.

]]> http://blogs.intel.com/intellabs/2010/09/16/justin_rattner_aims_to_change/feed/ 0 http://blogs.intel.com/intellabs/2010/09/13/how_love_lizards_and_sea_sickn/ http://blogs.intel.com/intellabs/2010/09/13/how_love_lizards_and_sea_sickn/#comments Mon, 13 Sep 2010 12:22:00 +0000 http://blogs.intel.com/research/2010/09/13/how_love_lizards_and_sea_sickn/ Read more >]]> When you think about Intel, your first thoughts may steer towards processors, the Intel bong or Jeffrey the robot. But yesterday, at the annual pre-IDF research press event, Intel researchers aimed to show another side – a growing side – of Intel that is focused on delivering the amazing and engaging user experiences of the future.

Genevieve Bell, Intel Fellow and head of the new Interactions and Experience Research Lab within Intel Labs introduced to the audience of more than 200 press and analysts that future success in technology rests in delivering user experiences that people love. Dr. Bell illustrated how the new lab will deliver amazing new experiences by beginning with understanding what people love about devices, platforms and services today, what technology can be applied to make that love even stronger and what technology can be applied to deliver new beloved experiences.

Understanding what people love begins with understanding people. Dr. Bell spent many of her formative years in the Australian Outback accompanying her mother who, an anthropologist herself, was studying the aboriginal communities. Amongst other feats of daring, Dr. Bell learned how to hunt lizards and extract water from frogs (that’s Dr. Bell in the middle). Those years watching her mother watch people and her own subsequent studies in anthropology helped cement the approach that Dr. Bell and her team take today.

Horst Haussecker, director of the experience technology lab within Dr. Bell’s lab, then presented his approach to developing the technology that underlies the experiences that Dr. Bell’s ethnographers and UI experts conceive. Horst’s team, along with other groups within Intel Labs such as the University partner labs in Seattle, Pittsburgh and Berkeley bring with them a varied background of expertise that is regularly called upon to deliver the amazing new interactions and experiences that will fundamentally shape our use of tomorrow’s technology.

Horst’s background itself could safely be called atypical of Intel engineers. While working on his doctorate in Physics at Heidelberg University, Horst took several opportunities to conduct mid-ocean research for weeks at a time. Aboard the research vessel Oceanus, amidst former marines who would gladly wrestle mahi-mahi on the boat deck and fighting the never ending rocking of the ship, Horst learned four key lessons that guide his teams approach to technology development today:

1. Solve real, not academic problems

2. Use an interdisciplinary approach to problem solving

3. You can do amazing things if you just try

4. Never vomit into the wind

OK, so maybe that last one is more of a life lesson than a guide to technology development.

The guests were then invited to view numerous examples of future user experiences that Intel Labs is working on today.

Several demos showcased various scenarios of surface computing where object recognition along with mini projectors and cameras are used to create dynamic new compute areas on virtually any flat surface. One such surface is the kitchen counter, where one day you may be able to simply place a food item on your counter and be provided with cooking instructions and how-to videos displayed directly on your counter. Or perhaps the system can be used to help children learn counting and coin denomination in the classroom.

There were also demos showcasing facial recognition. One researcher demonstrated the work Intel Labs is doing to optimize facial recognition algorithms to one day deploy the technology on mobile phones. Another researcher showed how that same software could be used in an automotive environment to provide driver recognition as a means of anti theft and to activate an advanced alert system in the event the user is not looking in the direction of an imminent yet avoidable impact.

Mobile augmented reality, a glimpse into how we may interact with the internet connected TV of the future and ray tracing on mobile devices for gaming were other key demos showcased at the event.

To hear more about how Intel approaches user interaction and experience research with Genevieve Bell and Horst Haussecker, listen below to the latest episode of the Future Lab podcast series from Intel Labs.

See more Intel Labs podcasts on ConnectedSocialMedia.com

]]> http://blogs.intel.com/intellabs/2010/09/13/how_love_lizards_and_sea_sickn/feed/ 0 http://blogs.intel.com/intellabs/2010/09/12/wolfenstein_gets_ray_traced_/ http://blogs.intel.com/intellabs/2010/09/12/wolfenstein_gets_ray_traced_/#comments Sun, 12 Sep 2010 19:00:00 +0000 http://blogs.intel.com/research/2010/09/12/wolfenstein_gets_ray_traced_/ Read more >]]> It’s this time of the year again: IDF! Time to show off the cool stuff our graphics research group has been working on. Today at the exhibition I demonstrated our new project called “Wolfenstein: Ray Traced”.

1) The visual content of the demo. The up-to-date Wolfenstein game is rendered through a real-time ray tracer with several special effects that haven’t been possible before in games with such an accuracy. Two of several highlights are:

•The chandelier model. Through ray tracing we are calculating physically correct reflections and refractions in the many glass objects it contains. The model is highly detailed with around one million triangles. This one model consists of three times the detail than everything else in the level combined. Have you ever seen something similar in a current game? Probably not, as with the traditional rendering approach it would not be efficiently doable.

•The surveillance station. At a wall in the game you see twelve screens that each show a different location of the level. This can be used by the player to get a tactical gaming advantage. Have you ever seen something similiar in a current game? Again – probably not.

2) The method how the demo runs. The images are rendered from a “cloud” of four servers with Intel’s Knights Ferry platform inside. You might have read (http://www.intel.com/pressroom/archive/releases/2010/20100531comp.htm) about this hardware before. It is a Many Integrated Core (MIC) architecture targeted towards the High-Performance Computing market (meaning: not targeted to the individual gamer to be bought). As ray tracing is a highly parallel application it can therefore take very good benefit of the many cores that are in a single chip on the Knights Ferry board. Once a chip in one of the servers has finished calculating a new frame for the game it will send it over the network to a thin client, in this case a small laptop.

Rendering high-end graphics for applications such as gaming in the cloud is an emerging trend that has some interesting advantages. Rather than being constrained to running these high-end applications only on your desktop at home, you can in principle play on any computer – such as a system at your friend’s house or even lightweight systems like a netbook or tablet. In the future, it could also free up compute resources on your system to be used for voice and gesture recognition, increasing the level of immersion for the application.

More screenshots are available at http://www.wolfrt.de .

The original Wolfenstein game has been made by id Software and Raven Software

]]> http://blogs.intel.com/intellabs/2010/09/12/wolfenstein_gets_ray_traced_/feed/ 13 http://blogs.intel.com/intellabs/2010/09/01/future_lab_radio_podcast/ http://blogs.intel.com/intellabs/2010/09/01/future_lab_radio_podcast/#comments Wed, 01 Sep 2010 13:22:07 +0000 http://blogs.intel.com/research/2010/09/01/future_lab_radio_podcast/ Read more >]]> What would it really take to communicate from a planet to the Starship Enterprise? Find out how Intel researchers and NASA are working to develop inter-planetary communication using Delay Tolerant Networking. Vint Cerf and Kevin Fall describe what the obstacles are and solutions they are researching in the latest episode of the Future Lab Radio podcast series.

Hear more Future Lab Radio on ConnectedSocialMedia.com

Future Lab is a weekly online radio show devoted to technology research from Intel Labs, and its university and industry partners. The interviews introduce you to a range of fascinating people on the front lines of research in areas like computing, biology, anthropology, energy, transportation, visual sensing, robotics, communication and more.

]]> http://blogs.intel.com/intellabs/2010/09/01/future_lab_radio_podcast/feed/ 0 http://blogs.intel.com/intellabs/2010/08/30/elegant_solutions_for_complex/ http://blogs.intel.com/intellabs/2010/08/30/elegant_solutions_for_complex/#comments Mon, 30 Aug 2010 08:00:00 +0000 http://blogs.intel.com/research/2010/08/30/elegant_solutions_for_complex/ Read more >]]> Intel Fellow, Radia Perlman, has been awarded the highest honor from ACM’s Special Interest Group on Data Communications (SIGCOMM) for pioneering contributions to Internet routing and bridging protocols. I had the good fortune to meet with Radia to talk about her research contributions and find out what she is up to these days. It was an unexpected surprise to also have her recite a poem she wrote in her dissortation!

Radia will receive the award and deliver the keynote address at the ACM SIGCOMM conference on August 31, in New Delhi, India.

]]> http://blogs.intel.com/intellabs/2010/08/30/elegant_solutions_for_complex/feed/ 1 http://blogs.intel.com/intellabs/2010/08/24/today_intel_along_with_nokia/ http://blogs.intel.com/intellabs/2010/08/24/today_intel_along_with_nokia/#comments Tue, 24 Aug 2010 11:59:07 +0000 http://blogs.intel.com/research/2010/08/24/today_intel_along_with_nokia/ Read more >]]> Today, Intel along with Nokia and the University of Oulu in Finland announced the establishment of the Intel and Nokia Joint Innovation Center. This lab will aim to revolutionize interactions with mobile devices by combining advanced mobile technology, 3D interfaces and user experience research. It will be based at the Center for Internet Excellence at the University of Oulu and as such will benefit from the research expertise at the University as well as the surrounding technical community.

The first research project the group is exploring is the development of rich, immersive internet experiences using 3D on a mobile device. This will apply software concepts originally developed for virtual worlds such as our ScienceSim collaboration and expand the benefits of 3D visuals beyond any single virtual world to enhance more of your everyday internet experience. Long term, the lab will explore what is possible or even desirable for these types of interfaces, to determine the right technologies to develop further.

This work is just beginning, but the team will soon begin to publish papers and present at technical conferences to share their findings over time. Much of the work will be developed under open source guiding principles and aligned with broader efforts around Meego.

Some of the challenges that virtual worlds have had in gaining broader adoption are the learning curve for mainstream users, processing requirements, and the so-called “walled gardens” that make it difficult to move between different worlds. If this collaboration is able to accelerate progress towards addressing these challenges, this could trigger an explosion in the number of websites that are 3D-enabled and create interesting new ways of communicating, sharing, learning and interacting through the Internet.

]]> http://blogs.intel.com/intellabs/2010/08/24/today_intel_along_with_nokia/feed/ 1 http://blogs.intel.com/intellabs/2010/08/16/intel_and_darpa_collaborate_on/ http://blogs.intel.com/intellabs/2010/08/16/intel_and_darpa_collaborate_on/#comments Mon, 16 Aug 2010 09:19:09 +0000 http://blogs.intel.com/research/2010/08/16/intel_and_darpa_collaborate_on/ Read more >]]> DARPA, the legendary research arm of the US Department of Defense, recently announced that it had funded Intel, along with three other organizations, to develop ubiquitous high performance computing (UHPC) prototypes for completion by 2018. Intel’s UHPC effort is unique in that DARPA and Intel are co-equal investors in the $49M research effort. The project will focus on new circuit topologies, new chip and system architectures, and new programming techniques to reduce the amount of energy required per computation by two to three orders of magnitude. In other words, from 100x to 1000x less energy per computation than what our most efficient computing systems consume today. Such dramatic reduction in power consumption will allow these extreme-scale systems to take full advantage of the increasing transistor budgets afforded by the steady advance of Moore’s Law. First postulated by Gordon Moore, Intel’s co-founder, the law observes that the number of transistors per chip roughly doubles every two years. If we fail to reduce the amount of energy per computation, we won’t be able to use all the transistors we can build, or won’t be able to operate all of them at anywhere close to their maximum speeds.

While the improvements in both energy efficiency and programmer productivity are intended to meet DoD’s rapidly growing performance demands of its vast sensor networks, simulation environments, and complex information systems, extreme-scale computing has broad application across the entire computing continuum. Let me give you two examples. First, consider the exascale supercomputers now being expected for late this decade by the HPC community. If we simply scaled one of today’s petaFLOPS supercomputers, which is capable of 10¹⁵ floating point operations per second, to exascale (10¹⁸ FLOPS) levels, we’d need a battery of nuclear power stations to supply its six gigawatts (6GW) of electrical power. With a useful limit of about 20 megawatts (20MW) of power in an HPC datacenter, we need roughly a 300x improvement in total system energy efficiency to build a practical and deployable exascale supercomputer. Second, consider an end-of-the-decade smartphone with extreme sensing capabilities requiring 100 gigaFLOPS of computing power. Without the anticipated breakthroughs in extreme-scale technology, such a phone would need a very, very big battery delivering 600 watts of instantaneous power. Think motorcycle battery and you’ve got the idea. Even if we could somehow deliver that much power, it would be very unpleasant to hold the phone, not to mention the battery, in your hand. If we are successful in developing the extreme-scale technology anticipated by the UHPC program, 100GF would consume a mere two watts of power or even less. We’re talking thin batteries and low case temperatures for one wicked-smart phone.

Intel’s UHPC Principal Investigator, which is DARPA-speak for the lead researcher, is Shekhar Borkar, an Intel Fellow and currently the head of the Academic Programs and Research unit at Intel Labs. Shekhar and his team are taking a fresh look at everything involved in designing extreme scale systems to be sure we can achieve DARPA’s goals of being both energy efficient in the extreme as well as being highly programmable. The challenges are great, but so is the talent Shekhar has assembled to attack them. Beside our own world-class circuits and systems researchers, Intel’s partners include top computer science and engineering faculty at the University of Delaware, the University of Illinois at Urbana-Champaign, the University of California, San Diego, as well as top industrial researchers at Reservoir Labs and ET International. Our UHPC program will also engage several leading manufacturers of compute-intensive systems, including SGI, Lockheed Martin, and Cray to review our work and help guide us to commercially practical, extreme-scale solutions. Other collaborators include Micron Technology on advanced memory chip design and Sandia National Laboratories on future applications development.

Extreme scale computing represents both an enormous challenge and an enormous opportunity to rethink the way we’ve been building computing systems since the advent of the microprocessor. We’ve had a relatively easy ride getting to where we are based on our ability to scale transistor size, but the road ahead is going to be much more difficult given the power constraints imposed by virtually every application from the smallest embedded devices to the largest supercomputers. The word frugal doesn’t begin to capture how efficient we’ll have to be in order to meet DARPA’s objectives for UHPC.

]]> http://blogs.intel.com/intellabs/2010/08/16/intel_and_darpa_collaborate_on/feed/ 3 http://blogs.intel.com/intellabs/2010/07/23/50g-link/ http://blogs.intel.com/intellabs/2010/07/23/50g-link/#comments Fri, 23 Jul 2010 16:53:10 +0000 http://blogs.intel.com/research/2010/07/23/50g-link/ Read more >]]> Fifty years ago, Ted Maiman built the first laser out of a ruby crystal rod, never expecting that this invention would revolutionize industries from medicine to communications. Likewise, it’s hard to imagine that Robert Noyce and Jack Kilby could have foreseen how their invention of the silicon Integrated Circuit (IC) – just one year earlier – would change the world.

Now in 2010, these two inventions are coming together with silicon photonics. We’ve been talking for many years about research to “siliconize” photonics, and until now all these breakthroughs have been at the device or component level. What we’ve announced today is for the first time we have an integrated silicon photonics transmitter using hybrid silicon lasers that’s capable of sending data at 50 gigabits per second (Gbps) across an optical fiber to an integrated silicon photonics receiver chip which converts the optical data back into electrical.

And what’s exciting is that this 50Gbps link is just the beginning. What we’ve demonstrated is the ability to integrate optical devices together, and just as we do in our microprocessor business (where we integrate more and more transistors together on a single chip), we will do so with silicon photonics. What does this give us? New functionality, new form factors, higher data rates, lower power and better performance than you could get with discrete photonic devices. Or to say it differently, this will allow us to apply optical technology to a whole bunch of new applications that could not have been possible previously. We now have the ability with integrated silicon photonics to bring low cost optical communications in and around the PC and server.

Why is this important? Let’s start with high end computing. Within servers, as demand for higher data rates increases, today’s copper interconnects require close proximity of processors, memory and IO. This limits, for instance, the amount of memory in the system to the number of modules (DIMMs) that can be mounted close to the CPU and or that can fit in the box. It also impacts the abililty to cool the system with many devices assembled so close together. Silicon Photonics will provide the ability to bring high speed optical communications into the platform, effectively relieving these distance constraints and providing the flexibility that could revolutionize system design. Servers could expand memory with remote, optically attached memory systems without sacrificing speed. I/O’s could run faster and with lower power if they were optimized for optical. Datacenters could maximize the performance of multi-core processors for large databases or virtualized environments with silicon-based optical links.

For clients, just imagine what 50Gbps could do. One could transfer an HD movie in less than 1 second. In that same second one could transfer 1000 high-res photos. Let’s look into the not too distant future of video displays. 3D TV’s are already hitting the market, doubling bandwidth requirements. Resolutions are increasing as well. Today 1080p seems sufficient on most TV’s – but imagine a screen that fills your entire wall, something you often see in science fiction stories. Imagine using that for a video call where the person you see literally appears to be in the room with you. To keep the same quality and resolution you will need Ultra High Definition (UHD, 4320p) – 16x the pixels of today’s HDTV. UHD at a 60Hz refresh rate requires 60Gbps, far beyond what we can do with copper cables, but easily within reach with integrated silicon photonics.

Today we have demonstrated 4 optical channels modulated at a rate of 12.5 Gbps each. These are combined and directed into one optical fiber for a total of 50Gbps. What’s next? Well, we can continue to scale up in line rate – we’ve already demonstrated modulators at 20 and 40 Gbps. We can also integrate more lasers or channels per chip. For example instead of 4 channels we can go to 8 or 16 channels. And when you add those two together, we can start talking about delivering data rates of 100G, 200G, 500G, and ultimately more than 1 Terabit per second (Tbps) – all out of a single integrated photonic chip smaller than your finger nail.

Today’s announcement represents a huge step forward in our research, but there is more to be done as we look to take this technology from research to commercialization. On the silicon front we will continue to optimize the performance of the integrated photonic devices. On the transmitter we will push to drive modulators to operate at lower operating voltages to minimize power consumption. We will also continue to improve the efficiency of hybrid silicon laser, again to minimize power consumption. As with everything we do, we must keep low cost, high volume assembly in mind. As such we are working on things like inline optical & electrical testing, more automated packaging and assembly techniques, and improved passive fiber connectorization approaches.

In summary, this milestone brings together two of the most important inventions of the past century: silicon manufacturing and the laser. Looking forward into the coming century, I expect that the world will evolve into one of wireless and optical: wireless when mobility is the driver and optical for any connection that demands very high data rates. Every manufacturer of a connected device in the future is going to have to start thinking about how high bandwidth, low-cost optical communications will benefit the products and services they deliver. This is the start of bringing optical communications to anyone, anywhere, connecting anything around the world using silicon based integrated lasers. To me, that’s exciting.

To find out more, listen to the Future Lab: Moving at the Speed of Light podcast

]]> http://blogs.intel.com/intellabs/2010/07/23/50g-link/feed/ 6 http://blogs.intel.com/intellabs/2010/06/28/revving_up_for_research_day_/ http://blogs.intel.com/intellabs/2010/06/28/revving_up_for_research_day_/#comments Mon, 28 Jun 2010 07:59:49 +0000 http://blogs.intel.com/research/2010/06/28/revving_up_for_research_day_/ Read more >]]> Researchers are having fun preparing for the 9th annual Research@Intel media event coming up this Wednesday, June 30th. Ever wonder how you’d get a vehicle on the 2nd story of a museum? Check out the time lapse video below, the Intel Labs team air lifts their version of the future Smart Car up into the Computer History Museum, and have some fun along the way.

The smart car will be on display Wednesday – showing off the labs version of virtuali in-car experience, that using netbooks and smart phones to connect to the vehicle over the Internet for remote engine start, adjust cabin temperature, access vehicle cameras for surveillance, lock/unlock doors and arm/disarm alarm. The futuristic car is also equipped with impact and proximity sensors, sends alerts to connected devices over the Internet when impact is sensed or an object is detected within surveillance zone. It can even detect other vehicles’ distance and objects in our blind spots to alert drivers and prevent accidents.

Mark your calendar for June 30th and watch Research@Intel Day in the video player at this blog, you can see the car in action.

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]]> http://blogs.intel.com/intellabs/2010/06/28/revving_up_for_research_day_/feed/ 0 http://blogs.intel.com/intellabs/2010/06/21/a_peek_into_researchintel_day/ http://blogs.intel.com/intellabs/2010/06/21/a_peek_into_researchintel_day/#comments Mon, 21 Jun 2010 14:26:04 +0000 http://blogs.intel.com/research/2010/06/21/a_peek_into_researchintel_day/ Read more >]]> Intel’s annual press event to showcase the latest in innovation from our labs is coming up June 30th, Research@Intel Day. If you can’t make this event in person, definitely visit this blog – and watch the viewer where a few of the lab’s projects will be broadcasted live that day, including a futuristic electric car and computers that read minds.

A few months ago, Rocketboom’s Elspeth Rountree visited Intel’s Pittsburgh Lab where some of the research is invented, a lot oft imes in collaboration with Carnegie Mellon University. Check out the video’s below – and you’ll get an idea of what Intel will show off next week:

]]> http://blogs.intel.com/intellabs/2010/06/21/a_peek_into_researchintel_day/feed/ 2 http://blogs.intel.com/intellabs/2010/06/21/what_buying_a_pc_means/ http://blogs.intel.com/intellabs/2010/06/21/what_buying_a_pc_means/#comments Mon, 21 Jun 2010 08:00:22 +0000 http://blogs.intel.com/research/2010/06/21/what_buying_a_pc_means/ Read more >]]> “In my social circle, I would take pride in owning a computer. People would look at me with respect.” Sushma is an Indian woman who is part of the “emerging middle class” in Bangalore. As we sat in her family’s modest living room, she told me what would motivate her to buy a PC. She’s one of the many people I interviewed in India who told me that the PC could have a transformational effect on her life. Not only could it help her get a job someday, help her learn more skills, help her children, and enable her to aspire to a higher socioeconomic class status, but owning one could also earn her a new respect among her peers. So why isn’t a young woman like Sushma, who is part of the ‘next billion’ customers, a proud owner of a new PC?

Strategies for introducing technologies in new markets historically and currently focus on “affordability” and “desirability.” Both are clearly important. But in addition to making technologies affordable and empowering to potential first-time buyers, our research revealed that making technologies socially viable–meaningfully connected to people’s lives and aspirations– is another crucial, yet often overlooked aspect of about what motivates people to adopt new technologies.

My colleagues Kathi Kitner, Scott Mainwaring, Dawn Nafus and I from Intel Labs’ People and Practices Research, spent the last two years systematically looking at and making sense of the social forces underlying technology adoption, how to link them to Intel’s core business objectives, and to make technologies relevant and meaningful to our end users.

To get the information we needed, we took grueling bus rides across the Russian-China border. We spent hours in houses eating meals with people around the world. We shopped at Walmart in Mexico and shadowed consumers in tiny grey-market PC and mobile phone shops in India We also met with government ministers in air conditioned offices in Kenya.

Bringing backgrounds in anthropology, psychology, public policy and international development, we spent hours conducting in-depth ethnographic interviews with existing and potential consumers across a range of socioeconomic and ethnic backgrounds. We listened to their narratives and desires. We saw how technologies fit (or did not fit) into the social contexts of their lives. We examined more than 30 cases of technology programs, services, and products around the world–and studied consumers, government policies and business strategies associated with them.

Through these experiences, we learned why technologies may seem appealing, yet out of reach for some people, and what ultimately drives someone to become a first time PC buyer.

We found something very interesting: that when you buy or use technologies, you are actually buying a new place in society: You’re fulfilling an aspiration for your children’s education and future; distinguishing yourself from those labeled as poor; or even buying yourself a sense of belonging as a global citizen.

Our research found that these powerful social forces are important drivers of technology adoption. They can make or break the success of technology programs, products or services. This means it’s imperative to find ways to engage with people’s aspirations towards personal growth and respect among their peers, as well as with goals of national progress when designing brand strategies, partnerships and business models. For example, this might mean rebranding a device targeted at “access for all” –so it does not make a person from the emerging middle class or lower income feel differentiated or labeled as “poor.”Or it may require repositioning an affordable device as “quality” so that first time buyers feel that what they are purchasing is a “‘respectable product” since it represents their first major entry into the technology world.

Many well-meaning technology programs fail because they don’t take these social forces into account. Time and again, we’ve seen projects fail because no attention was paid to how the program fits within the socio-cultural contexts of people’s lives. We’ve seen this with shared-access computing centers in India and Chile, infrastructure projects in Brazil, and countless government programs providing on-line access to services around the world.

There is a clear need for better tools to manage these risks. Based on our research, we developed something called the Social Viability Measure (SVM). It’s a tool to help Intel, governments, and international organizations who are introducing new technologies to people. The SVM is a three-step process to help decisionmakers develop a strategy for making technologies relevant and socially acceptable in people’s lives, while simultaneously maximizing business and social impact. We are piloting the SVM now with technology programs both internally and in the field.

We have culled all these findings into a major new report, “Reassessing ICTs and Development: The Social Forces of Consumption,” which was issued this month.

With these tools, when governments, businesses and multilateral organizations enter new market segments and service arenas or promote technology adoption, they will be better poised to hit the right social/economic forces to making those technologies relevant to their users. As a company that is committed to connecting and creating access for the “next billion” people to technologies, social viability is an important component to strategizing about how to accelerate technology adoption globally.

******************

To download the full report or to nominate a technology program to be considered as a potential pilot for the Social Viability Measure, visit the Social Viability Measure website.

]]> http://blogs.intel.com/intellabs/2010/06/21/what_buying_a_pc_means/feed/ 0 http://blogs.intel.com/intellabs/2010/06/10/live_from_researchatintelday_june_30/ http://blogs.intel.com/intellabs/2010/06/10/live_from_researchatintelday_june_30/#comments Thu, 10 Jun 2010 08:00:25 +0000 http://blogs.intel.com/research/2010/06/10/live_from_researchatintelday_june_30/ Read more >]]> Intel labs will soon be showing off some of the most exciting futuristic technology they are working on, at their annual Research @ Intel Day media event. Since not everyone will be able to make it in person, we’ll demonstrate the top projects live at this blog (on June 30th). Please mark your calendar and visit this link to catch a glimpse of the future through Intel labs “crystal ball”.

A few examples of types of things to expect:

Energy – from wireless power, to using your own body movements to “over-the-counter” sensors, how technology is going to enable consumers to become more informed of their energy consumption and manage it better.

Transportation – Intel Labs vision of the future “smart car”. A car will be on display equipped with the latest in research for transportation. An atom phone that controls temp and more, LED lights with the ability to communicate for accident avoidance, access to the cloud and if impact occurs, car records audio/video, and smart charging for energy efficiency.

New interface to computers – Goodbye Keyboard & Mouse. Hello: hand gestures, surface projection & mind reading. Intel Labs predicts all new ways of interacting with technology. At the event, experience speech recognition, robots, computers who read minds, and laptops, mobile phones using cameras that can recognize gestures and mini projection to turn regular kitchen tables into touch screens.

Cloud – research for visual and cloud computing, context awareness and how Intel plans to deal with the flood of data that is upon us. Includes a large 3D “wall” display with a rear projection screen and polarized glasses to allow an immersive experience for the audience

Platform Innovation – innovations in the labs for future Intel platforms, including virtualization, resiliency/circuits research, wimax platform power management and more.

There will be a live episode every hour on June 30th. Complete schedule is below (in pacific time). Please mark your calendar and join live here!

- 10:00am: Justin Rattner Welcome Keynote

- 11:00am: Transportation: the Future Electric Car

- 12:00 pm: Energy: Wireless power, power harvesting using human body movements

- 1:00 pm: User experience: mind reading, sensors and projection

- 2:00 pm: Cloud & Internet: Water Wars game and low power visual perception

]]> http://blogs.intel.com/intellabs/2010/06/10/live_from_researchatintelday_june_30/feed/ 0 http://blogs.intel.com/intellabs/2010/06/08/intel_completes_an_exa-scale_r/ http://blogs.intel.com/intellabs/2010/06/08/intel_completes_an_exa-scale_r/#comments Tue, 08 Jun 2010 12:44:47 +0000 http://blogs.intel.com/research/2010/06/08/intel_completes_an_exa-scale_r/ Read more >]]> Today Intel formally announced the third in a series of joint research centers focused on driving high-performance computing systems to exascale levels. Exascale means performance surpassing a billion billion computations per second — enough to hypothetically scan through every word ever spoken by humanity in about the time it took you to read this sentence.

These research centers are all new members of the Intel Labs Europe network:

- Exascale Computing Research Center, Paris (France) – December 2009

- ExaCluster Laboratory, Juelich (Germany) – May 2010

- ExaScience Lab, Leuven (Belgium) – today

Reaching the next level of supercomputing performance is about more than just reaching an arbitrary milestone. It’s about crossing many different thresholds of possibility that reside in the Exa-scale domain, to provide scientists and doctors new tools to draw new insights from of massive amounts of data. It’s about, along the way, developing the technologies that will one day allow the cloud to scale to level where massive distributed computers can simulate reality and synthesize “holodeck” like science-fiction experiences. And, over the long term, high performance tecnhologies become personal technologies — your PC today probably has more computing capability than a supercomputer from 20 years ago. Reaching exascale is about shaping the coming decades of computing.

These labs begin research as Intel unveils new plans for the Intel® Many Integrated Core architecture, which build upon Intel’s history of many-core related research including Intel’s “Larrabee” program and Single-chip Cloud Computer. Taken together, this represents a major effort from Intel to work with industry and academic collaborators to break down the barriers to unlocking truly phenomenal computing capabilities for the future.

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