Meet the Bloggers

Alexander Sterkin

Alexander Sterkin, has a M.Sc degree in from Moscow Institute of Radio-engineering Electronics and Automation, specializing in biomedical electronics and equipment. Alexander did his Ph.D. in Weizmann institute of Science of Israel in Brain Research, specializing in characterization of spatio-temporal dynamics of visual cortex activity. Currently Alexander is a Senior SW Application Engineer, of the Developer Relationship Division in Intel, his charter is SW enabling: Influencing world-wide leading software vendors; SW optimization and evangelism.

Alexandra Lyaplina

Alexandra Lyaplina holds a Masters degree in Economics and a Bachelors degree in International Relations. Alexandra has worked at various capacities within the Public Sector and Information & Communication Technology (ICT) industry, and has been with Intel Corporation for the past 3,5 years.

Ali-Reza Adl-Tabatabai

Ali-Reza Adl-Tabatabai is a Senior Principal Engineer in Intel’s Programming Systems Lab. He leads a team of researchers working on compilers and scalable runtimes for future Intel Architectures. Ali has spent most of his career building high-performance programming language implementations, including static and dynamic optimizing compilers and language runtime systems. His current research concentrates on language features that make it easier for the mainstream developer to build reliable and scalable parallel programs for future multi-core architectures and on architectural support for those features. Most recently he has worked on transactional memory, a new concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. Ali has published over 20 papers in leading conferences and journals. He received his PhD in Computer Science from Carnegie Mellon University.

Ansheng Liu

Dr. Ansheng Liu is currently a Principal Engineer with the Corporate Technology Group, Intel Corporation, Santa Clara, California, where he is developing silicon photonic devices and circuits for high speed optical interconnect and communications. He is one of the key contributors to Intel’s recent technology breakthroughs in fast silicon optical modulators and continuous-wave Raman silicon amplifiers and lasers. Before joining Intel in 2000, he worked at NASA Ames Research Center, Moffett Field, California; the National Institute of Standards and Technology, Gaithersburg, Maryland and at the University of Aalborg, Denmark as an assistant professor. His interests include nonlinear optics of nanostructures, near-field optics, opto-electronics, and photonics. He has authored or co-authored more than 90 publications in these fields and contributed to more than 40 patents. He was awarded the Intel Achievement Award and a Visiting Professorship at Sichuan University, Chengdu, China, in 2005. He has been a reviewer for various prestigious journals. He is the member of OFC/NFOEC 2007 and 2008 program committee. He has also been an invited speaker for various international conferences.

Dr. Liu received a B. S. degree in semiconductor physics from Sichuan University, Chengdu, China, in 1982, an M. S. degree in semiconductor physics from Zhongshan University, Guangzhou, China, in 1985, and a Ph. D. degree in physics from the University of Aalborg, Aalborg, Denmark, in 1992.

Bradley Whalen

Bradley Whalen joined Intel in 2011 as the Social Media Manager for Intel Labs; Bradley oversees all aspects of strategy and engagement in regards to social networks and web media pertaining to Intel Labs. Bradley also serves as the “Resident Filmmaker” for Intel Labs, crafting videos for the web that help showcase the innovative technology taking place at Intel. Bradley received an Associate’s Degree in Video Production in 2002 from Mt. Hood Community College and a B.S. in Business Administration, with a focus in Marketing & Advertising, in 2011 from Portland State University.

Brian Johnson

The future is Brian David Johnson’s business. As a Consumer Experience Architect he develops future products for the Intel Corporation. His responsibilities include researching, defining and mapping the public’s experience with future products and services. Before joining Intel, he served as executive producer on several interactive television deployments in Scandinavia, Europe and the United States for British Airways, The Discovery Channel and New Line Cinema’s The Lord of the Rings. Johnson speaks and writes extensively about future technologies in articles and scientific papers as well as in science fiction novels (Fake Plastic Love, the forthcoming This is Planet Earth) and short stories. He has directed two feature films and a commissioned painter. June 2010 will see the publication of his book “Screen Future: The Future of Entertainment, Computing and Devices we Love.”

Brian McCarthy

Brian is a technology evangelist in the Intel labs working to increase industry awareness of Intel’s future technology research and vision. Currently he works to evangelize the latest trends, strategies, and advancements in areas such as User Experiences and Interactivity, the Future of Transportation and Environmental/Eco research.

Bryan Casper

Bryan Casper is a Principal Engineer with Intel’s Circuit Research Lab, based in Hillsboro, Oregon. He leads Intel’s high-speed signaling research group responsible for the development and design of next generation mixed signal circuits, external memory and I/O systems. In 1998, he joined the microprocessor division of Intel Corporation and contributed to the development of the Intel Pentium and Xeon processors. Since 2000, he has been a circuit researcher, contributing to the development of external memory, mixed-signal self-test technology, signaling analysis methods, high-speed I/O circuit architectures and multiple I/O standards.

Changkyu Kim

Changkyu Kim is a research scientist in Intel’s Throughput Computing Lab, Santa Clara, California. His research interests include high-performance microprocessors, memory systems, and parallel processor architectures. Currently, Throughput Computing is a major priority for his research interest — analysis of emerging applications including database/data-mining, AI, physical simulation, and visibility computation with upcoming architecture trends, such as multi/many-core, GPU and heterogeneous computing. Before joining Intel Labs, Kim has the BS and MS degrees in computer engineering from Seoul National University, Korea. He received a PhD in computer science from the University of Texas at Austin.

Cheryl Miller

Co-editor of the Research@Intel blog, Cheryl is the Social Media Program Manager for Intel’s Corporate Technology Group and has taken on the role of videographer to showcase the cool research going on in the labs. She joined Intel in 2000 and has worked in various roles within the Corporate Technology Group for the last 5 years.

Daniel Pohl

Daniel is a research scientist at Intel Labs Advanced Graphics Group. He works on researching new algorithms to improve the quality and speed of computer graphics. Daniel is also responsible for developing demos to show off this work, visiting conferences and companies worldwide. He joined Intel in early 2007 after finishing his Master’s Degree in computer science at the University of Erlangen, Germany.

Divya Kolar

Divya Kolar holds a M.S in Computer Science conferred in 2006 from Portland State University. She joined Intel in 2005 and has previously worked as a Network Software Engineer where she was an active researcher in various security and manageability technologies like Intel® Active Management Technology. Today she is a Technical Marketing Engineer in the Intel’s largest research group and is responsible to promote Intel technologies to partners besides performing ecosystem enabling and competitive technology analysis for Intel Labs’ research.

Gabriela Gonzalez

Gabriela A. Gonzalez is a University Programs Manager for the Academic Program Office in Intel Labs and manages Intel’s strategic corporate partnerships with top US research universities and the Intel PhD Fellowship Program. In this position, Ms. Gonzalez is responsible for academic relationships and promoting Intel-sponsored academic programs. Prior to this role, she was a Process Engineering Group Manager at Intel’s newest 300mm Fabrication facility (Fab32) located in Chandler, Arizona. In this capacity, Ms. Gonzalez was a member of a team responsible for transferring the latest microprocessor technology from the development site to several production sites, and for ramping the high-volume manufacturing of Intel’s latest multi-core products, including 45nm and 32nm process technologies. She joined Intel as an industrial engineer in the Thin Films area and soon after was promoted to the engineering management ranks across Intel’s Arizona factories. Ms. Gonzalez holds a Master’s degree in Engineering and Manufacturing Management from Clarkson University and a Bachelor’s degree in Electrical Engineering from the University of Washington. She’s also currently pursuing a Ph.D. degree in Human and Social Dimensions of Science and Technology at Arizona State University.

Greg Leeming

Greg Leeming is an 11 year Intel veteran who is currently working in Intel Lab’s Academic Programs Research (APR) group where he is helping to launch the Intel Science and Technology Center (ISTC) Program and is leading the launch of the first ISTC, the Intel Science and Technology Center for Visual Computing (ISTC-VC). Prior to this role, he was assigned to the Semiconductor Research Corporation where he program managed the Focus Center Research Program, a large semiconductor research consortium involving 38 US universities. Greg has 27 years of industry experience working in research and new technology development organizations. He has a BS-Math from Bates College, Lewiston ME, BSEE from Northeastern University, Boston MA and an MSEE from Brown University, Providence RI. Greg spent an additional year in Brown’s PhD-EE program but was enticed out by a startup opportunity. Greg’s technical interests are in visual computing, cognitive computing and novel computing architectures.

Gregory Taylor

Intel Fellow, Corporate Technology Group
Director, Circuit Research Lab
INTEL CORPORATION

Greg Taylor is an Intel Fellow and director of the Circuit Research Lab in Intel’s Corporate Technology Group. He is responsible for research on low power and high speed circuits, high speed signaling, and enabling design and circuit technologies within Intel.

Taylor joined Intel in 1991 and has held several senior design engineering positions working on 10 generations of microprocessors including members of Intel’s Pentium® Pentium® II, Pentium® III, and Intel NetBurst® microarchitecture families. Prior to joining Intel, he worked as a principal engineer at Bipolar Integrated Technology.

Taylor is a Fellow of the Institute of Electrical and Electronics Engineers. He received his bachelor’s degree in computer and systems engineering in 1981 from Rensselaer Polytechnic Institute (RPI). He also received a master’s degree and doctorate in computer and systems engineering from RPI in 1983 and 1985, respectively. His graduate work was completed with the support of a Fellowship from the Fannie and John Hertz Foundation.

Guy AlLee

Guy AlLee is a computer industry veteran with over 25 years experience in computer architecture, hardware, and software. He is a Research Scientist in Intel Labs, Intel’s research arm, delivering breakthrough technologies that bring the benefits of the ongoing digital revolution to everyone. For the last serveral years he has been working on 380VDC for the Data Center. He recently moved to New Mexico to open Intel Labs’ New Mexico Microgrid Lab, part of the Energy Systems Research Lab which envisions the smart-grid with energy-smart homes and offices and neighborhoods as the next big inflection point since PCs, cell phones and the Internet. He holds a BSEE, an MSECE and is currently an ECE Doctoral Candidate at Portland State University.

Ife Hsu

In his 12+ years at Intel, Ife has worked primarily in technology certification focusing on quality and reliability aspects of boards/enabling ingredients (CPU sockets, Glue/Adhesive, LF solder, Low Halogen PCB, etc). Currently, in addition to his QRE lead role, he is also an Intel liaison for JEDEC JC14.x committee dealing with test methods and quality standards for solid-state devices. Prior to Intel, Ife worked at AT&R / NCR / Solectron with assignments ranging from network analysis, process automation, quality systems/auditing, server assembly, and test engineering. He holds BS degrees in mathematics, computer science from Lander University. BS in industrial engineering from Clemson University, and a MS in industrial/systems engineering from Georgia Institute of Technology.

Jeff Demain

Jeff is the Strategy and Business Initiative Director for Intel Lab’s Photonics Technology Lab. He works across the lab, external lab engagements and the Intel Business Units to drive the photonics research into product opportunities. He is also responsible for PTL’s outbound marketing initiatives. Prior to his current role Jeff worked on research and product development programs in the Enterprise Computing Group, the Super Computing Group, and the Assembly Technology Development Group. He gained his customer experience by leading a customer technical team in the field, and gained his marketing experience as Strategy and Executive Programs manager in Corporate Marketing for Intel’s Developer Forum.

Jeff holds a Bachelor of Science Degree in Computer Science from Arizona State University.

Jeff Parkhurst

Jeff Parkhurst is the Program Director for the ISTC Embedded Computing center. He is responsible for assisting the PIs in managing the operational details in each center as well as aiding in direction setting of the research. The Program Director is the primary liaison between Intel and the universities on all operational matters including contracts, IP, space, logistics, funding, and technology/knowledge transfer. Prior to this assignment, Jeff was an Academic Research Programs Manager working with senior technologists internal and external to Intel setting research directions for the design science areas of the Semiconductor Research Corporation (SRC). Jeff received his BS from University of Nevada at Reno in 1983 and his MS from the University of California at Davis in 1988 and his PhD at Purdue University in 1994. Dr. Parkhurst is the author of numerous papers and one patent.

Jeffrey Foerster

Dr. Jeff Foerster joined Intel in August 2000 as a Wireless Researcher with Intel Labs in Hillsboro, Oregon. He is currently a manager and Principal Engineer in the Communications Technology Lab (CTL) in CTG, primarily focusing on short-range wireless and related technologies, including Ultra-wideband (UWB) technology, 60 GHz radio systems, video/display compression techniques, and source-channel coding. He is also chair of the Intel PHY Communications Research Council which reviews and approves grants to universities in the optical, RF circuits, and communications systems areas.

Jerry Bautista

Jerry Bautista is the Director of Technology Management for Intel’s Microprocessor Research Laboratory and is chartered with driving the transfer of the lab’s research into product development and helping to set Intel’s strategic research agenda for future microprocessors. He co-leads the Intel Tera-scale Computing Research program, driving technologies for highly parallel, compute intensive applications and platforms. In addition, he leads a cross-Intel effort to explore memory/interconnect bandwidth challenges/solutions for future server and client platforms. Previous to joining Intel, Jerry was the CTO of an optical device start-up and spent 13 years at Lucent Technologies in the field of optical components and communication systems/networks, with assignments ranging from basic research (at Murray Hill Bell Labs) to development, operations and strategic marketing. He received his B.S. from Stanford University and PhD from Princeton University.

Jim Held

James Held leads a virtual team of senior architects chartered with developing the architectural framework and research roadmap for the Corporate Technology Group’s Tera-Scale Computing Research. Visit Jim’s corporate bio to find out more about him.

Joseph Pitarresi

Smart Car Technology Strategist at Intel Labs, Integrated Platform Research, Connected Vehicle Innovation. Currently guiding the strategy for an extensible client to cloud architecture with vehicle related cloud services.

Justin Rattner

Justin Rattner is an Intel Senior Fellow and director of Intel’s Corporate Technology Group. He also serves as the corporation’s chief technology officer (CTO). He is responsible for leading Intel’s microprocessor, communications and systems technology labs and Intel Research.

In 1989, Rattner was named Scientist of the Year by R&D Magazine for his leadership in parallel and distributed computer architecture. In December 1996, Rattner was featured as Person of the Week by ABC World News for his visionary work on the Department of Energy ASCI Red System, the first computer to sustain one trillion operations per second (one teraFLOPS) and the fastest computer in the world between 1996 and 2000. In 1997, Rattner was honored as one of the Computing 200, the 200 individuals having the greatest impact on the U.S. computer industry today, and subsequently profiled in the book Wizards and Their Wonders from ACM Press.

Rattner has received two Intel Achievement Awards for his work in high performance computing and advanced cluster communication architecture. He is a longstanding member of Intel’s Research Council and Academic Advisory Council. He currently serves as the Intel executive sponsor for Cornell University where he serves on the External Advisory Board for the School of Engineering.

Rattner joined Intel in 1973. He was named its first Principal Engineer in 1979 and its fourth Intel Fellow in 1988. Prior to joining Intel, Rattner held positions with Hewlett-Packard Company and Xerox Corporation. He received bachelor’s and master’s degrees from Cornell University in Electrical Engineering and Computer Science in 1970 and 1972, respectively.

Kapil Sood

With over 17 years in technology development, Kapil is driving strategic mobile technologies and industry enabling standards and architectures at Intel. Kapil is a Research Scientist at Intel Labs, and serves as Security Architect for Intel’s emerging ultra low power mobile platforms and multi-core systems. Kapil is the Technical Editor of the Ecma TC32-TG21 “Network Proxy” standard, and contributor to CSCI Client Power Management. Kapil received IEEE recognition for his contributions in publishing IEEE 802.11r (Secure Fast Roaming) standard, and has significant security contributions at IEEE 802.11w (Protected WLAN Management), 802.11z (WiFi Video) and emerging 802.11ad (60 GHz) standards. His current research includes Smart Grids Security and Networking.

An entrepreneur and technologist, Kapil was Director and Architect for startup Corrent, designing Security ASICs for optical networks. Kapil was Principal Engineer at AGCS (bought by Lucent), where he designed the ROAMEO GSM/3G cellular system, ClientCare multi-media Service Provider Contact Center, and previously on the design team of Motorola IRIDIUM.

Kapil has MS Computer Science (ASU), MBA (UoP), and BS Computer Science (IT-BHU, India). Kapil has multiple patents, published papers, open-source contributions (Linux, OpenSSL, OpenCryptoki), and is a frequent conference speaker.

Karen Tanenbaum

Karen Tanenbaum is a graduate intern in the design group of the Interaction & Experience Research lab at Intel Labs. She is also finishing her PhD at the School of Interactive Arts & Technology at Simon Fraser University in Vancouver, BC, where her dissertation research is focused on interaction design for tangible and ubiquitous computing. She helped coordinate Intel’s presence at the 2012 Maker Faire Bay Area and is working on research projects related to wearable computing, interactive narrative, design fiction, and the Maker and Steampunk movements.

Limor Fix

Limor Fix is the director of Academic Programs and Research (APR) at Intel. APR is the primary university-facing division of Intel Labs. APR funds a wide variety of research grants at universities around the world. These grants range from small seed funds to large academic Intel Science and Technology centers. APR also leads Intel’s academic relation with universities and government. Limor has a PhD in computer science from the Technion, Israel. After graduation, she conducted post-doc research at Cornell University and in 1994 joined Intel. Limor led a major change in Intel’s validation technology and methodology. She developed innovative formal verification system that has been widely adopted by Intel’s design teams. In this role, Limor led the development of a new formal specification language, ForSpec, that was donated by Intel to Accellera/IEEE and had a major impact in the IEEE-1850 standard. Limor also co-led the Intel’s research lab that was located at Carnegie Mellon University and had developed leading technologies in machine learning, vision, micro-architecture and other disciplines. Limor has published more than 30 papers, she is the co-author of the book “Electronic Design Automation for Integrated Circuits handbook”, she served as the general chair for the Design Automation Conference, the premier conference for VLSI design tools and methodologies and she currently serves on the board of directors of CRA (Computing Research Association).

Maria Bezaitis

Maria Bezaitis became Director of Intel’s People and Practices Research Group in June 2006. Previously she held management positions in marketing and research at Apopleo, Inc., a wireless strategy and network integration firm based in Chicago. Prior to that, she spent four years leading ethnographic research teams and developing the Advanced Research competency at Sapient Corporation, a business consulting and technology services firm. She started her professional career at E-Lab, a firm that pioneered the use of ethnography for product and service development, where she was a managing partner.

Bezaitis has written and presented on topics including collections & seriality, photographic images and identity, the role of social research and design for technology innovation and development. Bezaitis earned a B.A. in French Literature from Dartmouth College and a Ph.D. from Duke University, in French Literature and Cultural Studies.

Link to official bio

Mario Paniccia

Dr. Mario J. Paniccia is an Intel Fellow and director of the Photonics Technology Lab. He joined Intel in 1995 as a lead researcher developing a novel optical testing technology for probing transistor timing in microprocessors. Paniccia currently directs a research group in the area of Silicon Photonics. The team is focused on developing silicon-based photonic building blocks for future use in enterprise and data center communications.

In 2008 Paniccia was named by R&D Magazine as “Scientist of the Year” for his team’s pioneering research in the area of Silicon Photonics. He has received two Intel Achievement Awards and has published numerous papers, including three Nature papers, three Nature Photonics papers, three book chapters, and has over 67 patents issued or pending. He is a fellow of the IEEE, SPIE and OSA.

For more information on silicon photonics, visit www.intel.com/go/sp

Markus Wiengartner

Markus Weingartner is Intel Press Programs Manager for Europe, Middle East and Africa based in Munich, Germany. He is responsible for developing and managing Intel’s technical press programs in the EMEA developed and emerging markets. He is also managing all Technology and Manufacturing Group, Intel Labs and Intel Labs Europe related press programs in the EMEA region. Before Markus joined the Intel EMEA public relations team he was an Intel application engineer where he worked together with ISVs on software optimization/development projects for the first Intel Pentium® 4 Processor and its follow-on processors. Markus assumed his current role in June 2002.

Prior to joining Intel in February 2000, Markus attended the Munich University of Applied Sciences in Germany. He holds a degree in Electrical Engineering (Data and Information Technology).

Ravi Sahita

Ravi Sahita is a Senior Researcher in the Communication Technology Lab in Intel’s Corporate Technology Group. Ravi is currently working on platform approaches to address computer security issues. Ravi has contributed to Intel® AMT, Intel® NetStructure® products and the open sourced Intel® Common Open Policy Services (COPS) client SDK. Ravi is a contributing member of the Internet Engineering Task Force (IETF) and the Trusted Computing Group (TCG) standards bodies. He received his B.E. in Computer Engineering from the University of Bombay, and an M.S. in Computer Science from Iowa State University.

Renee Kuriyan Wittemyer

Renee Kuriyan is a research scientist in Intel Corporation’s People and Practices Research group. She holds a PhD from the University of California, Berkeley focused in development studies. She has a Masters degree in Public Affairs from Princeton University’s Woodrow Wilson School with a focus in international development and science and technology policy. She has extensive experience conducting research on a range of technology and development topics in emerging economies. This includes projects with the World Bank, United Nations Development Program, NGOs, and Microsoft Research India. Her current research focuses on the cultural politics of consumption, the middle class and globalization. She continues to conduct research on the political economy of information and communication technologies and development (ICTD).

Rich Uhlig

Richard Uhlig is an Intel Fellow and chief architect for Intel’s Virtualization Initiative. Uhlig started virtualization efforts within Intel in 1998 as a research project in the Corporate Technology Group (CTG) and has since led the definition of multiple generations of virtualization architecture for Intel processors and platforms, known collectively as “Intel Virtualization Technology” (Intel® VT). Intel VT is today used in a variety of settings and applications to improve the utilization, management, availability, and security of systems based on Intel Architecture. Visit Rich’s corporate bio to find out more about him

Roy Want

Roy Want is a Principal Engineer at Intel Research Santa Clara, California, and leader of the Ubiquity Group. He is responsible for exploring long-term strategic research opportunities in the area of Ubiquitous & Pervasive Computing. His interests include mobile computing, wireless protocols, hardware design, embedded systems, distributed systems, automatic identification (RFID), and micro electromechanical systems(MEMS).

Want received his BA in computer science from Cambridge University, UK in 1983 and continued research at Cambridge into reliable distributed multimedia-systems. He earned a PhD in 1988. While at Olivetti Research (1988-91) he developed the Active Badge, a system for automatically locating people in a building. He joined Xerox PARC’s Ubiquitous Computing program in 1991 and lead a project called PARCTab, one of the first context-aware computer systems. More recent projects have included applications of electronic tagging and the design of PDAs that use manipulative user interfaces, such as the Hikari project. At PARC Want managed the Embedded Systems Area and earned the position of Principal Scientist. He joined Intel in 2000 and is currently exploring the concept of Dynamically Composable Computing, a paradigm that utilizes short-range wireless connectivity to seamlessly share nearby resources, enabling an effective mobile computing experience. The concept is a revolutionary approach that could change the way we use mobile computers.

Want is also the author, or co-author, of more than 50 publications in the areas of mobile and distributed systems; and also holds 53 patents. He is very involved in the research community through program committees, invited talks at conferences, and is Editor-in-Chief for IEEE Pervasive Computing. He is also a Fellow of both the IEEE and ACM.

For recreation he is a keen runner, hiker and skier. He has completed 3 marathons, and orienteers when his young family allows. A more complete summary of his work can be found at http://www.speakeasy.org/~roywant/vita.htm.

Sean Koehl

Sean is a technology evangelist in the Intel labs working to increase industry awareness of Intel’s future technology research and vision. Currently he works to evangelize the latest trends, strategies, and advancements in areas such as “Tera-scale” many-core processors, silicon photonics, and emerging “immersive connected experiences” such as virtual worlds and augmented reality.

Sean joined Intel in 1998 as an engineer working on silicon optical debug and spent the next five years contributing to the design, packaging and research of silicon devices for Intel’s Photonics Technology Lab. Later, as a Senior Technical Marketing Engineer, Sean worked to educate the public on Intel’s breakthroughs in the area of silicon photonics. Sean received a B.S. in Applied Physics from Purdue University and holds five patents in the area of silicon-based optoelectronics.

Shekhar Borkar

Shekhar Y. Borkar is an Intel Fellow, and Director of Academic Programs & Research within Intel Labs. Borkar is responsible for directing research in technologies for Intel’s future microprocessors.

Borkar joined Intel in 1981. He worked on the design of the 8051 family of microcontrollers, iWarp multicomputer and high-speed signaling technology for Intel supercomputers. Borkar is an adjunct member of the faculty of the Oregon Graduate Institute. He has published over 60 articles and holds 41 patents.

Borkar was born in Mumbai, India. He received a master’s degree in Electrical Engineering from the University of Notre Dame in 1981, and a master and bachelor degrees in Physics from the University of Bombay in 1979.

Sriram Vangal

Sriram Vangal is a Principal Researcher with Advanced Microprocessor Research at Intel Labs and with Intel since 1995. He was the technical lead for the research team that designed the industry’s first single-chip 80-core, sub-100 W Polaris TeraFLOPS processor (2006), the 48-core Rock Creek prototype (2009) and the first near-threshold voltage (NTV) Claremont IA processor (2011). His research interests are in the areas of low-power high-performance circuits and energy-efficient computing. He has published 25+ journal and conference papers and has 16 issued patents with eight pending. He holds a Ph.D. degree in electrical engineering from Linköping University, Sweden.

Stefano Pellerano

Stefano Pellerano was born in Bari, Italy. He received the Laurea Degree and the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2000 and in 2004, respectively. During his Ph.D., his activity was focused on the design of fully integrated frequency synthesizers for wireless LAN applications. In 2003 he has been a consultant with Agere Systems (former Bell Labs) in Allentown, PA. He is now with the Communications Technology Lab of Intel, Hillsboro, OR. His recent research interests include fully-integrated MIMO transceivers, mmWave radios and digital-style phase-locked loops for WiFi/WiMax applications in CMOS technology.

Stephan Herhut

Stephan Herhut is a Research Scientist at Intel Labs in Santa Clara where he works for the Programming Systems Lab on improving programmability of parallel architectures. Stephan’s research interests include language design, program optimization and concurrent systems. In particular, he is enthusiastic about increasing programmers’ productivity without sacrificing performance goals. Lately, he is working to bring the performance of parallel hardware to JavaScript while keeping the spirit of web programming.

Before joining Intel, Stephan held the position of a Research Fellow at the University of Hertfordshire, UK, where he worked on a high-productivity, high-performance language for numerical applications. Stephan holds a Ph.D. in Computer Science from the University of Hertfordshire, UK, and an M.Sc. in Computer Science from the University of Kiel, Germany.

Timothy Mattson

Tim Mattson earned a PhD. for his work on quantum molecular scattering theory (UCSC, 1985). This was followed by a Post-doc at Caltech where he worked on the Caltech/JPL hypercubes. Since then, he has held a number of commercial and academic positions with high performance computers as the common thread. Application areas have included mathematics libraries, exploration geophysics, computational chemistry, molecular biology, and bioinformatics.

Dr. Mattson joined Intel in 1993. Among his many roles at Intel, he was applications manager for the ASCI teraFLOPS project, helped create OpenMP, founded the Open Cluster Group (with it’s cluster package, OSCAR), and launched Intel’s programs in computing for the Life Sciences.

Currently, Dr. Mattson is conducting research on abstractions that bridge across parallel system design, parallel programming environments, and application software. This work builds on his recent book on Design Patterns in Parallel Programming (written with Professors Beverly Sanders and Berna Massingill and published by Addison Wesley). The patterns provide the “human angle” and help keep his research focused on technologies that help general programmers solve real problems.

Tomm Aldridge

Director, Energy Systems Research lab at Intel corporation. The lab is chartered to perform long term research related to the generation, distribution, distribution and control of energy as related to Intel’s practices, products and the eco-systems they impact.

Vijay Kesavan

Vijay Kesavan is a researcher at the Communications Technology Lab, Intel Research and Development. He has worked on various wired and wireless networking research projects and products in Intel. His is currently focusing on next-generation mobile broadband technologies. He has previously worked on seamless handovers in mixed network and has worked on the design and architecture of Ethernet switches, routers and network processors. He holds a Masters degree in Electrical Engineering, from Michigan State University.

Vinay Phegade

Vinay Phegade is a security researcher and architect in Intel Labs. His research interests are developing security solutions to protect user’s online identity and transactions. He has been working at Intel since 2000.

Vu Nguyen

Vu Nguyen is a Technology Evangelism Manager in Intel Labs working to increase industry awareness of Intel’s future technology research and vision. Currently he works to evangelize the latest trends, strategies, and advancements in areas such as Worry-Free Computing, the Future of Transportation, Context-Aware Computing and Immersive Experience research.

Wen-Hann Wang

Wen-Hann Wang is vice president of Intel Labs and director of Circuits and System Research for Intel Corporation. Prior to his current assignment, he served as vice president of the Software and Services Group (SSG) and general manager of Software and Solutions and Product Development in China. While in SSG, he also held general management positions for the Core Software, the Managed Runtime, and the Middleware Products divisions. He was also instrumental in establishing SSG’s presence in PRC.

Learn more at Wen-Hann’s executive biography

Yorgos Palaskas

Yorgos Palaskas received the Diploma in Electrical and Computer Engineering from the National Technical University of Athens, Greece, in 1996, and the M.S. and Ph.D. degrees, both in Electrical Engineering, from Columbia University, New York, in 1999 and 2002, respectively.

Since 2003 he has been with Intel Labs, Hillsboro, Oregon, where he is currently an engineering manager. During 2003-2005 he worked on integrated MIMO transceivers and power amplifiers for WiFi. Since 2006 he has been leading research projects on digital-style, SoC compatible, WiFi, WiMAX and LTE radios in heavily scaled CMOS processes, and also research on 60GHz radios for multi-Gb/s wireless communications. He has published more than 40 papers at IEEE journals and conferences, 1 book chapter, and has 17 patents issued and several pending. He is currently serving on the Technical Program Committee for the IEEE International Solid-State Circuits Conference and the IEEE European Solid-State Circuits Conference.