Wireless connectivity is a prerequisite in most user devices today, from laptops, to phones, tablets, e-readers, etc. Usually radios reside on a separate die from the application processor, resulting in bulkier devices. Integration of the radio and application processor would enable smaller form factors for slimmer devices (maybe even miniature wearable devices), and can also reduce the cost of the overall solution. The low cost of such integrated processor+radio platform can further enable a host of new applications towards the vision of the “internet of things” where devices such as home appliances, sensors, etc communicate with each other, exchange information and can be actuated remotely.
However, integration of the radio together with the application processor is not a trivial task. Application processors move quickly to the next available CMOS process to take advantage of the increased density afforded by CMOS scaling and Moore’s law. This pace is very difficult for RF circuits to maintain: conventional RF design requires accurate transistor models which can take a long time to develop, and the radio might need multiple spins and tweaking to meet performance targets. Conventional RF circuits can also suffer from lowering supply voltages, worse inductors, etc as CMOS technology scales. To top it all off, integration of the radio together with noisy digital circuits can significantly degrade the radio performance e.g. due to disruption of the sensitive voltage-controlled oscillator (VCO) used to generate the accurate radio signals.
Intel Labs has been working on techniques to overcome these issues and allow integration of radios inside large SoCs (System-on-Chip) in the most advanced CMOS nodes. Paper 9.4 presents a digital transmitter for WLAN implemented in 32nm. The power amplifier of the transmitter operates as a digital switch, which has two important implications that resonate across much of our work: (1) the performance improves with CMOS scaling like a digital circuit (while RF circuits usually get worse), and (2) the design does not need mature/accurate RF models. The power amplifier was in fact designed with no RF models very early on in the life of the 32nm process. To be able to operate with such a switching 0-VDD power amplifier, the amplitude information of the OFDM signal is generated by adding two constant-amplitude phase-modulated signals: when these signals are in phase the amplitude of the sum is high, and when they are out-of-phase the amplitude is low. Paper 9.4 introduces a digital phase modulator architecture that can deliver, for the first time, OFDM bandwidths of up to 40MHz required for high rate 802.11n WiFi. The phase modulator uses inverters loaded by capacitors to introduce the signal information, making for a completely digital and scaling friendly design (no inductors!). The complete 32nm transmitter achieves state of art power efficiency which is even expected to improve further with further CMOS scaling.
- Transmitter and ModulatorAnother key block of a wireless radio is the Local Oscillator Generation (LOG). This block is usually added after the sensitive VCO to protect it from unwanted interferers. For example, the LOG can be used to offset the frequency of the Power Amplifier from the VCO to minimize disruption of the very sensitive VCO block (disruption is maximum when PA and VCO operate at the same frequency). Conventional LOG circuits sometimes use multiple inductors and can be very application-specific. Paper 20.6 introduces an all-digital LOG architecture optimally suited for SoC integration since it consists entirely of elementary digital building blocks: flip-flops, simple logic gates and delay lines (again, no inductors!). In addition to its simplicity, the architecture is reconfigurable, which allows the same hardware (LOG and importantly VCO) to be shared between different wireless standards (e.g. WiFi and WiMAX) that would normally require duplicate hardware. The reconfigurability of the LOG is also particularly interesting in the context of SoC interference. For example if an SoC interferer appears close to the radio frequency (e.g. a clock whose frequency is varied to reduce power dissipation), the LOG can quickly reconfigure itself to protect the VCO and preserve signal fidelity.
The last radio paper from Intel Labs, paper 3.4, takes the integration challenges of radios inside large SoC to the extreme: it shows, for the first time, a WiFi radio integrated in a complete PC-on-a-chip comprising dual-core Atom processor, PCIe, DDR3, PMU, etc. Interference mechanisms between the radio and the rest of the PC have been mitigated properly at all relevant levels, e.g. RFIC, package, etc. Measured radio results show state of art performance even when the PC is in full operation. This research indicates that interference mitigation techniques together with the scaling-friendly digital radio architectures of the previous papers could enable new levels of integration, time-to-market and cost targets, creating new opportunities and applications for devices that will “connect and enrich the life of every person on earth”.