In my previous blog I wrote about four papers being presented at ISSCC next week that contribute to our efforts in Tera-scale Computing. Today, I’d like continue scanning through the ISSCC abstracts and highlight four other papers, which I’d categorize as examples of “Intelligent Circuits.”Fundamentally, digital circuits are at the heart of nearly every form of machine intelligence today. However, the qualities that we consider “intelligent,” the ability to perceive, learn, and adapt would usually be found at higher layers of the computer architecture. As sophisticated processors find their way into to more and more devices, often with strict space and power requirements, we are finding that we have a need for our circuits to be smarter, to adapt to their environment and user needs. The first example of this adaptability is seen in a pair of papers that describe a prototype processor that uses resilient circuits to enable “extreme” operation. This means either running at ultra-low, near threshold voltages for low power or overclocking to ultra-high frequencies to improve performance. Usually, a processor is limited in minimum voltage or maximum clock speed because at some point when circuits are pushed too far, errors begin to occur. However, even when pushed beyond the normal limits (called guardbands) these errors don’t happen often. If you catch them and correct them you can continue to push the circuits. This is very common for I/O circuits, but relatively new for processor logic and memory. The first of the two papers describes the core logic of the resilient design: “A 45nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance.” It shows that one can gain more than 20% performance by reducing guardbands and effectively overclocking the chip. The second paper, entitled “PVT-and-Aging Adaptive Wordline Boosting for 8T SRAM Power Reduction” describes a resilient memory (cache) to go along with the resilient core. When turning voltages down it is actually the on-chip SRAM memory that tend to fail first, not the processor logic. So, this prototype incorporates “charge pumps” that boost the voltages on these SRAMs when they are vulnerable to errors – i.e. during memory reads and writes. This allows the overall processor to run a much lower voltage. The prototype showed up to a 27% reduction in power consumption using this technique. Take a look at this video for a demonstration of this resilient technology. The next paper “A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) Reconfigurable Transceiver in 45nm CMOS” describes a “universal” transceiver for system I/O. The goal of this work is to create a single transmitter (TX) and receiver (RX) pair that could be used to support almost any type of I/O in an enterprise platform, from board-to-board I/O in a server rack to chip-to-chip I/O within the box, from standard copper wires to next generation optical fibers. The transceiver can reconfigure to change voltages, speeds (5-25Gb/s), signaling methods, and the equalization technique used to account for noise during transmission. The end result of this approach could be a simplified approach to system I/O that helps reduced costs through the re-use of a single TX/RX design for many applications. Finally, “A 320mV-to-1.2V On-Die Fine-Grained Reconfigurable Fabric for DSP/Media Accelerators in 32nm CMOS” describes a flexible accelerator that could speed up a variety of tasks in future mobile SoC chips as well as high-end tera-scale systems. The prototype is a fabric of basic elements which can be reconfigured on-demand, transforming itself from one type of accelerator to another. Our researchers have shown that it can process apps from image processing to text searches and a variety of digital signal processing tasks at much higher efficiency than CPU (as much as 2.6 trillion operations per watt). It also can scale down to ultra-low voltage operation to 0.3V to support battery-conserving modes on future mobile devices.
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