Enforcing Moore’s Law through Technology Research – Part 3

Welcome to the third installment! I’ve been blogging about research progress towards making compound semiconductors mainstream and talking about both challenges and opportunities.

Enforcing Moore’s Law, Part 1

Enforcing Moore’s Law, Part 2

In this blog, I’ll update the progress and give a look ahead to some of the upcoming research projects.

First as a reminder, unlike silicon, a compound semiconductor is made up of two or more elements, indium, gallium and arsenic for example (InGaAs). Using two or more elements means more opportunity to tune the materials for performance or optical properties but also makes the challenge of fabricating wafers and processing much more complicated. Today, compound semiconductors are used in smaller scale applications where their special properties outweigh the added costs. Our goal is to take advantage of the vastly larger spending on silicon infrastructure and put it to use fabricating compound semiconductor devices.

I gave five individual challenges which needed to be solved in order to allow broader use of compound semiconductor technology and we are working both internally as well as with external groups such as universities to make progress on this list:

- Build compound semiconductor devices on silicon substrates. That would allow us to reuse the highly refined silicon infrastructure including 300mm wafers and down the road gives us the option of integrating a few specialized devices with a sea of silicon devices. [progress reported at IEDM 2007]

- Find a suitable high K gate dielectric. Due to the different surface, the silicon high K solution won’t work as is but we can leverage knowledge we gained to help guide us. [progress to be reported at IEDM 2009, Ref. 1]

- Build a high performance PMOS device to go with the existing NMOS. This is needed to have power efficient CMOS logic though some special circuits can get by with just one type. [progress reported at IEDM 2008]

- Build enhancement devices. Most existing work is based on depletion mode where you apply a voltage to shut them off. Power efficiency demands that those devices be normally off. [progress reported at IEDM 2007]

- Make them small enough to compete with silicon transistor densities. If we stop at integrating only a few specialized devices then this is not needed but then we also won’t reap the full benefit of the technology.

The last blog focused on item #3, using strain to increase the mobility of the P-channel and we were able to achieve 5x mobility improvement over strained silicon by adding ~2% biaxial strain to the material. We have an upcoming paper at IEDM 2009 [Ref. 1] which reports progress on item #2, finding a suitable high-k dielectric.

Most silicon devices today are MOS (Metal Oxide Semiconductor) devices where the controlling gate electrode is separated from the conductive channel by a thin oxide layer. A thinner oxide gives greater control of the channel but also can create higher leakage as the current tunnels through the thin layer. Our implementation of high-k with metal gates allows the channel to have great control while suppressing leakage currents by up to 100x compared to a gate dielectric with the same electrical thickness. This in turn gives best in class transistor performance.

By contrast the highest performing III-V devices are not MOS devices. Generically they are quantum well field effect devices (QWFET) where the quantum well is created with a very thin (~10nm) high-mobility layer sandwiched between two high resistance barriers. Because the quantum well is undoped and its interfaces are smooth, scattering is suppressed, and charges can move very quickly.

EnforceFig1.JPG

The channel is still controlled by the gate electrode (field effect) but the separation is via a Schottky contact. The reason people built gates this way is that thin oxides with the required high quality don’t natively grow on III-V surfaces. Since these are compound semiconductors, there are two or more elements at the surface and these react at different rates. What you get is a mixture of states, irregularities, and ultimately poor performing devices. However use of a Schottky contact means that when the barrier is thinned, the gate leakage current goes up exponentially.

EnforceFig2.JPG

Last year’s IEDM had a whole session devoted to fabrication of III-V MOSFET’s with high-K dielectrics and had a good mixture of both basic material science as well as engineering. There are multiple techniques for cleaning the surface of any native oxide; the trick is to then get the right dielectric down without creating interface traps. Some possibilities include 1) in situ clean + direct dielectric deposition, 2) clean + surface passivation + dielectric deposition, 3) clean + thin transition layer + dielectric deposition, and each of these has many choices for chemistry and materials. Our paper results are using technique 3, and we’ve introduced two new materials into the stack bringing up to seven unique materials in order to make it work. We also have a second paper in this year’s IEDM [Ref. 2] which benchmarks these devices against their silicon competition and shows they perform better for a range of lower voltages which translates to power savings.

Recapping the challenge list:

- We have demonstrated we can build N channel quantum well devices on a silicon substrate with equivalent performance to those grown on III-V substrates

- We can modulate the device operation to act as an enhancement device, not just depletion

- We can integrate high-k dielectrics on N-channel and still get good performance

- We can make a fast P channel device to go with the N channel device

Some work in progress:

- These devices are still very big. While there’s been some good work to make short channels and self-alignment (e.g. at MIT), we will likely need a new device architecture to improve the density to compete with silicon

I’ll illustrate the problem with a SEM of one of our previous devices.

EnforceFig3.JPG

In this figure the gate appears as a very narrow line while all the other structures are very big. In part this is large to make it easy to measure but there are also hidden challenges to making it smaller. Creating the quantum well suppresses interactions outside the well which makes moving charges into and out of the QW harder (=high equivalent resistance). Making contacts large hides this issue. So another material challenge is to engineer a contact structure which minimizes the barrier between the metallic contact and the QW. A second challenge is to predict/measure what happens when the device becomes small in three dimensions. This is still a classical device but there are strong quantum-mechanical effects that need to be considered.

If we can make all of the material integration challenges happen and also make dense devices then III-V technology could replace silicon technology starting around the middle of the next decade. There is still much work to be done to achieve this but stay tuned for further progress.

Ref. 1: M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, W. Rachmady, U. Shah, and R. Chau, “Advanced High-K Gate Dielectric for High-Performance Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications”.

Ref. 2: G. Dewey, R. Kotlyar, R. Pillarisetty, M. Radosavljevic, T. Rakshit, H. Then, and R. Chau, “Logic Performance Evaluation and Transport Physics of Schottky-Gate III-V Compound Semiconductor Quantum Well Field Effect Transistors for Power Supply Voltages (VCC) Ranging from 0.5V to 1.0V”.

2 Responses to Enforcing Moore’s Law through Technology Research – Part 3

  1. Paul Brunemeier says:

    Mike,
    as someone who worked on AlGaAs and pseudomorphic HEMT’s fresh from grad school, I’m a fan of the work you and your team have done on III-V channel FET’s on Si. The work is superb, and your blogs are a great read.
    Someday soon, these transistors will need to be integrated in order for the work to realize its full potential. I’d like to ask if there is any knowledge yet on the robustness of these structures to temperature or other stresses presumably imposed during interconnect processing–such as lower-level metal CVD or PECVD ILD dep.
    thanks,
    Paul