“Powering” the Energy Efficiency Revolution

Intel Labs have been on the forefront of energy efficiency research for well over a decade. Our rich set of technologies, spanning circuit, architecture, and platform, is powering an exciting revolution.

Beyond Intel Labs’ past breakthrough in intelligent clock gating, ultra low voltage, and low leakage circuits, we have been solving a growing dynamic variation problem. Variations caused by thermal fluctuations, voltage drooping, and transistor aging demand conservative circuit operating guardbands. Processors run slower and consume higher power as a result. Our researchers have invented resilient techniques and deployed novel monitoring and error-correcting circuits that allow the removal of all guardbands. We have implemented a complete processor using these resilient circuits and demonstrated it at 2009 Fall IDF. Our measurements on this functioning processor show a solid 37% power reduction.

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Our power architecture research aims at reducing the mismatch between power delivery and power demand of the platform. Peak high power requirement constrains design of battery and power adaptor (BRIC). It forces compromises to ensure they can supply up to certain wattage when needed but still often fall short of true peak demand such as turbo mode. Intel Labs’ researchers came up with a novel super capacitor augmented power architecture to address this problem. Super capacitor is a dense storage capacitor added to power delivery architecture to provide temporary power during short, peak demand cycles. It decouples CPU from battery/BRIC and allows CPU to achieve full turbo mode. It also provides much flexibility in battery design.

While circuit techniques and power architecture provide interesting contributions to energy efficiency, we found compelling opportunities in platform level power optimization. For example, we explore the possibility of having a low-power network agent offload insignificant activities and provide more opportunities to put the main platform to “sleep”. We found that this innovation has the potential to save billions of dollar energy cost yearly.

Our researchers further took a holistic approach in managing power across the platform. First, we focus on aligning and coordinating platform activities to create longer idle periods where we can aggressively reduce power. Second, we explore fine grain control over subsystems across the platform. This enables us to quickly and easily power down elements of the platform not in immediate use and not critical to the compute task at hand. Finally we make sure that software and hardware collaborate seamlessly in realizing fine-grain power saving potential. Our research show that we can get to 50X idle power reduction on Moorestown platform compared with a previous generation platform.

In summary, our research enable running circuits at 37% less active power, reducing platform idle power by 50X, saving billions of dollars in energy cost and providing much more flexibility in future battery design and energy density innovation. It powers the energy efficiency revolution and plants the seeds for many more excitements to come.

3 Responses to “Powering” the Energy Efficiency Revolution

  1. Thomas Jackson says:

    I’m a 12th-grader and I’m working to comprehend technical reading. It helps that you write such posts. Thank you.

  2. Peng Zeng (Illinois Tech) says:

    Thank you for sharing the Intel’s progress in this field. It’s pity not attending in person. I am carrying out research on low power design and management too. Will you please to post some paper references as result of this research? Thanks!