A famous American philosopher (lets call him FAP in the time honored Intel acronym tradition) once famously said that “It’s hard to predict anything, especially the future.” Here I attempt to take on FAP through the prism of ISSCC; the annual International Solid-State Circuits Conference that takes place every February, deep in the windowless bowels of the San Francisco Marriott.The conference itself is a highly successful, if rather austere affair, where chip designers of all stripes come to strut their stuff. There is none of the usual frippery one associates with professional meetings, no conference banquets, no guided tours or vendor booths (technical books being the only exception). Your steep registration fee gets you a glass of water (no ice) at break times, and the obligatory conference proceedings. That’s it. It is also an exceptionally precise affair with strict rules about font sizes, color schemes on your foils, time limits and general professional bearing. Oh and I almost forgot, attendees are treated to the sight of each session chair silently stalking the aisles, doing head counts during every single paper presentation. They keep statistics of this sort of stuff. About the only real entertainment to be had is to watch the occasional author squirm, under polite, but pointed post paper questioning. Standards are very high, professional reputations are on the line, and you definitely don’t want to show up unprepared. Nevertheless, the occasion remains a heady mix of imaginative dreamers and precise technicians who keep things interesting and dare I say, fun. Most major advances in our industry have premiered in the conference and acceptance of one’s work at ISSCC has been a hoary rite of passage for generations of chip design professionals. Intel has always had a strong presence and this year was no exception, with 15 presentations. In addition to premiering Nehalem; our presentations spanned a wide range, from memory (SRAM, Flash) and wireless components, to thermal sensors and optical interconnects. The microprocessor session had 4 Intel papers detailing our entire 45nm product line. Much of this has been covered elsewhere and I won’t say more. The session was distinguished by the almost total absence of any one else from the industry (NEC being the exception). Whatever the reasons, one hopes that it is not the beginning of a trend. Competition keeps you sharp, and its absence is missed. This year also saw Mark Bohr, Intel Senior Fellow, as the second instance (the first was Pat Gelsinger) in the last 10 years, of a plenary speaker from Intel. He gave a quick and lucid review of the golden age of transistor scaling through the 90′s, where area reduced by 50% and voltage scaled by 30% like clockwork. Life was good. Designers rode this wave, surfing and occasionally hiding behind the 50% power reduction that 30% voltage scaling gave us. That era has run its course, to be replaced by a more complex regime where, as Mark says, “Material and structure innovation (like our Hi-K metal gate) is as important as dimension scaling.” Voltage scaling has slowed to a barely perceptible crawl, and low power demands loom large. It is no accident that the end of the voltage scaling era was also the beginning of a new multi core and SOC era. Moore’s law continues, chip sizes decrease and transistor counts increase, but fundamentally different challenges face designers in this new regime. Mark’s plenary talk was a clear description of these challenges and its many real opportunities. A spirited and occasionally moving plenary talk by John Cohn, an IBM Fellow, followed. Dressed for laughs in full mad scientist regalia (tie dyed lab coat no less), and accompanied by the obligatory Van de Graff generator (remember the frizzy hair folks?), he made three important points: (1) The profession of engineering is viewed very negatively across the board. We trail scientists (our close intellectual cousins), by a whopping 3 to 1 in most measures of positive influence; (2) Young people are increasingly motivated by societal/environmental/energy efficiency concerns. They don’t see anything useful emanating from the engineering field in any of these areas, and; (3) Engineers need to be involved in re-establishing an emotional connection with our customers as well as future entrants into the profession. Perception is often reality and we ignore these trends at our peril. The emotional connection with our customers is especially important. Witness the success of Apple in a difficult macro-economic environment. The center of gravity of most of the work from industry was clearly 65nm. There were few 45nm designs and fewer still (4 including 2 from Intel) at 32nm. Both of Intel’s 32nm papers (on SRAM’s and thermal sensors) were more mature (with real yield results) than anything else on that node. Our technology lead, relative to the rest of the industry, widens as more and more companies go fabless. The trend towards SOC is relentless but the pace is varied across market segments. In contrast to microprocessors, all of our target growth markets (consumer electronics, embedded and MIDs) were well represented with innovative designs from a slew of competitors. A clear eyed and well executed mixed signal SOC integration story from the cable modem space, was a good example. Everyone is mired in cost/power reduction efforts, where the subtext is the incumbent (non IA) SOC ecosystem, but the optimizations are all around the periphery, i.e. the media processing and mixed signal blocks. This is a clear and compelling opportunity for Intel, given our process advantage and the potential of an IA based SOC. The semiconductor revolution has reinvented and transformed entire industries, like computing and communications. Doing the same in the energy, automotive, health care and environmental industries will have equally profound and positive consequences. This has clearly not gone unnoticed, with well attended and interesting contributions in energy harvesting, sensor interfaces and silicon based drug delivery systems. Working examples of microwatt mechanical energy harvesters and CMOS micro pipettes for in vitro drug delivery were clear evidence of that heady mix of dreams and precision. Finally, if you are a glutton for punishment, you can attend the late night sessions (they go on until 10PM), where post dinner naps are rudely interrupted by talks on thermal energy harvesters, wireless power delivery and other such cheerful topics. I learned that you can now buy a module that harvests 2mW of electrical energy from about 4W of heat flux. It doesn’t sound like much, but it is not hard to envision completely self powered systems communicating at low duty cycles and low data rates with this sort of source. Our Seattle lab is exploring a similar phenomenon with their WISP and WARP technology. The industry is clearly trying to establish that elusive emotional connection with consumers and is struggling to translate this into an actionable silicon challenge. So what is the future going to be? I can do no better than to fall back on our old friend the FAP who also famously said: “When you see a fork in the road, take it” Cheers Soumya P.S. FAP is of course the inimitable Yogi Berra. If you want to take a look at the ISSCC proceedings your best bet is to go to IEEE explore in a few months when they will be posted online. Some of the papers can be heavy going for the non specialist, but many are surprisingly accessible. They are mercifully short (unlike this blog), and are limited to one page.
Connect With Us
Tags#IntelR&Dday @idf08 Big Data Cloud Computing Ct CTO energy efficient Future Lab Future Lab Radio HPC IDF IDF2008 IDF 2010 Immersive Connected Experiences innovation Intel Intel Labs Intel Labs Europe Intel Research ISSCC Justin Rattner many core microprocessor mobility multi-core parallel computing parallel programming radio Rattner ray tracing research Research@Intel Research At Intel Day Robotics security silicon silicon photonics software development Stanford technology terascale virtual worlds Wi-Fi WiMAX wireless