I attended ISSCC this week, the first time in many years that I’ve attended. It was a smaller affair than I remembered, driven I’m sure by recent events. Those same events colored much of the discussion in the hallways. Clearly companies everywhere are searching for greater efficiencies and focusing their efforts. Inside the paper sessions things were more upbeat, but shared the themes of greater efficiency and a focus of effort.Two of the plenary talks directly touched on how engineering can make the world a greener place. René Penning de Vries, the CTO of NXP Semiconductors, started out by showing that energy and power management is about more than battery life. Using electronics to intelligently manage consumer appliances that tend to run continuously, such as PCs and TVs, can lead to significant power reductions. This in turn will be a significant contribution to future energy conservation and reduction of greenhouse gases. In the last plenary talk John Cohn, an IBM Fellow, gave an inspirational presentation on the perceptions of engineers among students and the decline in engineering degrees granted in the US every year. Looking back at historical engineering graduation rates he showed that Sputnik clearly inspired a surge in engineering enrollment and graduation that lasted for decades. That ended in the eighties and enrollments have been declining for the past 20 years. Declining enrollments are driven by the choices that individual students make and most graduating students won’t even consider a career in engineering, many without even knowing what an engineer really does. We are now facing new global technology challenges in the areas of climate change and energy efficiency. Can these crises play the same role that Sputnik did more than 50 years ago and stimulate resurgence in interest in solving technological problems? John passionately believes that engineers should get out into schools and show kids that engineering is about creativity and solving important problems, and not just about math and hard work. Although, admittedly, engineering does involve some math and hard work. The theme of increased efficiency carried forward through many of the sessions and papers presented at the conference. Microprocessor papers emphasized the need to increase performance without increasing the power dissipated in a single socket, whether that socket is in a server, desktop, or laptop system. Many of the highlights from Rajesh Kumar’s “A Family of 45nm IA Processors” also had a power efficiency oriented theme. Nehalem required that any new features added to the microprocessor yield more than 1% performance for additional 1% power, a higher standard than had been used in the past. The addition of power gates to the Nehalem core allows the standby leakage of the cores to be virtually eliminated when they are inactive, in a manner that is transparent to both the platform and software. This transparency ensures that this capability is regularly turned into actual power savings for the end user. In the same session Hideaki Saito presented on “A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors”. He described a 3 dimensional integration approach, stacking a memory die directly on top of a microprocessor die offering significant size and delay reductions. While such stacking using through silicon vias has been described before, they added a new twist by making the memory reconfigurable. If you want to play back a movie, then the memory can be partitioned so that it is one large memory connected to the hardware video decompression unit. Later it can be partitioned into a collection of smaller memories that are each dedicated to serving different portions of the system on a chip, enabling you to listen to music while reading through all of the e-mail that arrived while watching the movie. In a similar vein Yasufumi Sugimori presented “A 2Gb/s 15pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking”. This is another 3 dimensional integration approach that gives short range wireless a new meaning. They used coupled inductors to send signals between stacked die, across a distance of 120 µm. This coupling avoids the need for the through silicon vias in the previous approach, saving the cost of this wafer processing step. The range of the inductive coupling is short enough that messages need to be relayed to get from the bottom to the top of the stack of chips, a capability that they included. They estimated that the power spent communicating through the stacked chips was only half of what is spent in today’s stacked chip packages, while the area spent on communication circuits was reduced 40 times. Thermal sensor papers talked about the parallel challenges of measuring on die temperatures on increasingly aggressive digital process technologies. Why? In order to improve the power management capabilities of microprocessors by providing more accurate information to that power management unit that Rajesh Kumar mentioned. A paper presented by Himanshu Kaul “A 300mV 494GOPS/W Reconfigurable Dual-Supply 4-way SIMD Vector Processing Accelerator in 45nm CMOS” talked about a very power efficient calculating engine. Operating at very low voltage this circuit ran eight times more efficiently than it did at more normal voltages. This high efficiency was obtained by carefully shutting down idle portions of the calculations while running others just fast enough to get the job done. This can be applied … A technology for low power (energy) computation, media being one possible application. Many of the same ideas were touched on by Yu Pu of NXP Semiconductors in his paper “An Ultra-Low-Energy/Frame Multi-Standard JPEG Co-Processor in 65nm CMOS with sub/Near-Threshold Power Supply”. Overall it was a very interesting conference, showcasing some ideas that can help us to deal with the energy and climate challenges that face our society, as well as a call to action for engineers to play a part in ensuring that there will be more engineers available to continue to deal with these problems in the future.
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