Digital technique to calibrate radio components down to 1/10’000’000’000’000 of a second

Radios are used extensively today to access the internet on the go; for example, WiFi is present in virtually all new laptops today. One of the key components of a radio is the high-frequency oscillator that is used to generate the frequency at which the information is transmitted, like 101.1MHz for an FM channel on your car radio. This component is very sensitive and can be easily disturbed by the power amplifier (a power amplifier is used to amplify the signal before it is transmitted by the antenna). To make sure that the power amplifier does not interfere with the oscillator, it is necessary to offset their operating frequencies.

This can be done using a frequency divider, a high frequency block that receive a signal at its input at a specific frequency and produces an output signal at a different frequency, i.e. divided down by 1.25 times. If, for example, we want to transmit at 2.5GHz for a WiFi wireless radio, now the oscillator can operate at 2.5×1.25~3.125GHz. This frequency will be different from the one transmitted by the power amplifier at 2.5GHz, eliminating interference problems (fig. 1).


However, the signal generated by the divider has to be extremely pure, meaning that it should only contain the desired tone at the main frequency (2.5GHz). Any other “spurious” frequency content should be 60dB lower (1’000 times lower amplitude) that the main signal at 2.5GHz. Just to give an idea of how small these spurious tones have to be, imagine that if the main signal amplitude is equivalent to the Empire State Building in New York City, these spurious tones have to be smaller than a fire hydrant (fig. 2)!


The output signal of a typical divider by 1.25 like the one used in this work looks like in Figure 3. Variations and mismatches in the fabrication process result in a small error Δτ appearing in the waveform every 4 cycles of the output (in fact this effect generates a spur at one-fourth the frequency). This error would have to be less than 100fs to achieve the required 60dB signal purity. Achieving such small timing errors is not trivial in today’s scaled CMOS technology. This is where digital-intensive techniques come in to save the day… Thanks to the device miniaturization, digital design can be very small and consume little extra power when compared to the rest of the radio, but still be able to “make-up” for the other component imperfections.


To be able to calibrate the divider and achieve this level of performance, we needed to measure timing errors (fig. 3) as low as the required 100fs. In fact our technique was able to go as low as 20fs. This is an incredibly small quantity…imagine that if we could stretch 20fs to the time needed to snap your fingers, then one second would last more than 1.5 million years, approximately the time from human appearance on earth to today (fig. 4)!


Using this technique, we were able to calibrate one of these dividers to achieve the required signal purity. In Figure 5, the frequency content of the signal generated at 2.5GHz is shown before and after the calibration. You can see how the spurious tones are reduced more than 60dB below the main one (at 2.5GHz).


2 Responses to Digital technique to calibrate radio components down to 1/10’000’000’000’000 of a second

  1. Fabio says:

    I can appreciate the importance of the achievement (also thanks to the funny analogies) but absolutely nothing is said about the methods, except for a couple cryptic notes about “digital techniques” and “measure timing errors”. I can understand the need to keep details undisclosed (it’s a commericial value to preserve, I guess), but I have to say that the information provided with this post is very close to zero…
    In any case, congratulation for your great achievements, Stefano! Great job!

  2. Stefano Pellerano says:

    Dear Fabio,
    Thanks for your interest!
    I agree with you, the technical details on this post are minimal. However, it was meant to be like this, since this post is not addressing a highly technical audience. The main goal is to share some of the latest research achievements in a more “informal” way, create interest and fuel people curiosity.
    If you are interested in the technical aspects of the work, please look into my paper published in the proceeding of 2009 International Solid-State Circuit Conference (ISSCC). It is an IEEE publication.