Last summer I wrote about compound semiconductors, both challenges and opportunities.In this blog, I’ll update the progress and give a look ahead to some of the potential paths for use. First as a reminder, unlike silicon, a compound semiconductor is made up of two or more elements, indium, gallium and arsenic for example (InGaAs). Using two or more elements means more opportunity to tune the materials for performance or optical properties but also makes the challenge of fabricating wafers and processing much more complicated. Today, compound semiconductors are used in smaller scale applications where their special properties outweigh the added costs. I gave five individual challenges which needed to be solved in order to allow broader use of compound semiconductor technology and we are working both in internally as well as with external groups such as universities to make progress on this list: - Build compound semiconductor devices on silicon substrates. That would allow us to reuse the highly refined silicon infrastructure including 300mm wafers and down the road gives us the option of integrating a few specialized devices with a sea of silicon devices. progress reported at [IEDM 2007] - Find a suitable high K gate dielectric. Due to the different surface, the silicon high K solution won’t work as is but we can leverage knowledge we gained to help guide us. - Build a high performance PMOS device to go with the existing NMOS. This is needed to have power efficient CMOS logic though some special circuits can get by with just one type. - Build enhancement devices. Most existing work is based on depletion mode where you apply a voltage to shut them off. Power efficiency demands that those devices be normally off. [progress reported at IEDM 2007] - Make them small enough to compete with silicon transistor densities. If we stop at integrating only a few specialized devices then this is not needed but then we also won’t reap the full benefit of the technology. The last blog focused on item #1, fabricating III-V devices on silicon substrates. Stated another way, what we are after is leveraging the orders of magnitude higher spending on silicon process tools and factories so that there is a much lower hurdle to introduce the technology. Items #3 and #4 on the list similarly drive leveraging silicon design tools and for this blog I’ll focus on item #3, building a high performance P channel device to go with the N channel. Today’s silicon technology is based on CMOS (Complementary Metal Oxide Semiconductor) but it hasn’t always been that way. Past silicon generations included NMOS or PMOS where the N and P refer the charge of the carrier within the channel (negative or positive). With those technologies we eventually hit a power wall and then Moore’s Law scaling continued with new CMOS technology. The C means complementary and in a typical circuit the N channel device is back to back with a P channel device. That configuration means one device is on while other off and CMOS is much better for static power than either NMOS or PMOS alone. In an ideal world we would figure out how to make CMOS III-V’s or at least be able to copy the beneficial attributes of complementary devices. Most research on III-V materials and devices has focused on N channel because the mobility of the electrons (negative) is much higher than that of holes (positive). Higher mobility means less voltage is required to move the charge and in turn you get a higher performance device. A typical N channel example is shown here where a 30x higher electron mobility translates to a 10x improvement in relative power vs performance. Unfortunately holes have 20-100x worse mobility for most III-V materials contrasted with silicon which has only about 3x difference. If you aim to write a research paper, it is a lot more rewarding to write about the fast N channel and neglect the P. We can make the P mobility higher by copying a technique from silicon processing, add strain to the material. Strain works by changing the band structure to favor a population of light holes instead of the mixture of heavy and light holes in unstrained material. In silicon, our leading edge processes increase the P channel mobility by about 3x and that closes the gap to N channel. In silicon we can apply strain at the edges of the channel and see the benefit. For our very thin quantum well structures we need to grow them on a mismatched lattice to introduce strain. As discussed last time, mismatch can lead to dislocation defects so it is a delicate balance. We will be showing our results at the upcoming IEDM in December but for now here is a graph showing more than 5x mobility improvement over strained silicon by adding ~2% strain to the material. The milestone here is the use of strain to significantly improve hole mobility in III-V P channel and in turn creating a high performance device. Here is a top down view of the III-V quantum well device with a 40nm gate length. Recapping the challenge list: - We have demonstrated we can build N channel quantum well devices on a silicon substrate with equivalent performance to those grown on III-V substrates - We can modulate the device operation to act as an enhancement device, not just depletion - We can make a fast P channel device to go with the N channel device Some work in progress: - There’s been good research done in the last year on modeling surface preparation and exploring different cleaning techniques in preparation for adding a high-k dielectric (e.g. at Purdue). Achieving high-k will allow us to start calling our devices MOS. - These devices are still very big. While there’s been some good work to make short channels and self-alignment (e.g. at MIT), we will likely need a new device architecture to improve the density to compete with silicon Predicting the past is always easier than predicting the future. It is easier to explain why III-V’s today are not used as broadly as silicon and harder to see where they might be used in the future. Nevertheless I’ll try using our challenge list as a starting point. If we are able to put III-V devices on the same chip as a sea of silicon devices, then we can add the unique capability that III-V’s bring to existing product designs. For example, RF chips today use III-V’s for high frequency performance and adding this technology to silicon might allow use of multiple radios with better power and performance. Similarly III-V’s are more efficient at emitting light than silicon and adding optical interconnects to a silicon chip would (in principle) become easier. The progress to date is sufficient to start asking what those products would look like and whether they are better than solutions we have today. If we can make devices that act like conventional CMOS circuits and we can make them on silicon, then we can consider devices which have III-V’s used in blocks for either high performance or in blocks with low operating voltage (0.5V vs 1V for silicon) and mix them with the more dense silicon transistors. Products build on this process should be very useful for handheld devices as the low power blocks would extend battery life in addition to the integrated radio advantage. If we can make all of the above and also make them dense then III-V technology could replace silicon technology starting around the middle of the next decade. There are many challenges to overcome to achieve this but stay tuned for further progress. Mike Mayberry is Director of Components Research with Intel’s Technology & Manufacturing Group. Components Research does process technology research.
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