Voltage and power reductions in our products come from a broad engagement between process, design and architecture. For our latest 45nm products, the careful design of the SRAM cell and our invention of high-k metal gate transistors were key contributors to reducing minimum voltages. Previously, I wrote about the Climate Savers Computing Initiative and our research to achieve efficiency gains at the platform level.Beyond energy efficient design lays the notion of powering our processors and chipsets over a much wider range of voltages. Let me share with you some important research we have underway that may lead to dramatic improvements in the dynamic operating range of our products. Ever wonder why we don’t keep lowering the operating voltage for a processor or chipset in order to reduce power? As new markets, our customers, and end users demand low-power processors, every possibility is fair game, right? Unfortunately, manufacturing variations cause memory cells to become unreliable at low voltages. In a large memory structure, such as a cache or a register file, a small number of these cells require relatively higher voltages to function correctly. The minimum voltage at which the entire chip can reliably operate is referred to as Vcc-min. A small number of memory cells typically limit Vcc-min and, consequently, limit the operating range of our products. Since reducing the supply voltage has a quadratic effect on the power consumed by the microprocessor, Vcc-min is a critical design parameter where low power operation is the goal. Reducing Vcc-min and enabling products to operate with lower supply voltages will allow each of our designs to address market segments where ultra-low power operation is an asset. In this manner we enable a much wider dynamic voltage range for our products. A wider dynamic voltage range makes our platforms more adaptive, with the ability to deliver maximum performance at high voltage when needed or the best MIPS/watt at low voltages when the platform is at or near idle. In our circuit and microarchitecture labs, researchers are working on techniques that allow our designs to reliably operate at much lower voltages than they do today. Our microarchitecture lab is focusing on an architectural approach to the Vcc-min problem. The goal of this work is to develop adaptive memory structures that maximize performance when performance is most important (high voltages) while still enabling low voltage operation at a small performance loss when energy efficiency is most important. A good example of this approach is the versatile smart cache which incorporates a feature that we proposed recently at the International Symposium on Computer Architecture called “word-disable.” The versatile smart cache is constructed with standard memory cells (SRAM or register file), a small number of which will fail at low voltages. To enable low voltage cache operation, word-disable identifies the words in the cache that contain these failing memory cells and then disables and excludes these sections from use. Since the versatile smart cache is constructed with standard memory cells and the entire cache is available for use, word-disable has minimal overhead when operating at high voltages. Word-disable causes a small performance penalty during low voltage operation due to the loss of cache capacity that results from disabling parts of the cache. Our circuit research lab is approaching the Vcc-min problem from a different angle: making adjustments to the basic circuit cells to allow for minimization of Vcc-min (with minimal impact on basic cell size). To investigate this research, we designed, fabricated and took measurements from a 1.2V, 65nm video encoding motion estimation chip that we showcased at the International Solid-State Circuits Conference and at our Research at Intel Day event last month. Ultra-low supply voltages would reduce the noise margins and reliability across process SKUs, especially affecting weak keeper devices, such as flip flops. One design improvement to avoid this issue is increasing the channel length of transistors in transmission gates and opportunistically increasing full-interrupted keepers. This, combined with only allowing single stage multiplexers with a maximum of two inputs, improves circuit robustness at ultra-low voltages. Usage of lower supply voltage regions requires the use of voltage level shifters. Instead of using the standard single stage topology, a two-stage cascaded split-output level shifter was implemented. This topology enabled more robust low power operation, allowing reductions of 20% in total energy. Using more robust level shifters, sequentials and datapath logic, this research chip was able to achieve a very wide dynamic range. In testing, it exhibited a voltage range from 230mV to 1.4V. This translated into a dynamic power range from 14.4 microwatts (at 4.2MHz) to 82 milliwatts (at 2.4 GHz) – a factor of nearly 5700x! With more and more customers asking for products with a wide dynamic range of operation, these techniques may prove vital to our future low-power and energy-efficient products.
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