Stefano Pellerano on 60 GHz Radios

Wireless is cool. But nobody wants a slow wireless connection. However, fast wireless means large bandwidth and in today’s crowded spectrum bandwidth is a scarce resource. Recently, 60GHz radio (often referred to as mm-wave radio) has attracted the attention of the wireless communications community for very wide-band application opportunities. Why 60GHz? First, there is a huge amount of unlicensed spectrum available around there. Second, if we think of the bandwidth as a fixed percentage of the carrier frequency, 10% of 60GHz would give 6GHz, compared to 250MHz at 2.5GHz. With channels larger than 2GHz, applications with data rates over 5Gb/s over relatively short distances (i.e. 10m) are possible. Wireless Personal Area Networks (WPAN), wireless HDMI, synch & go and wireless docking station are just a few examples of what could make mm-wave technology attractive for the high-volume consumer market. Moreover, low-cost technologies like CMOS are already proving to deliver the performance required to build a reliable millimeter-wave wireless link.

Fractional-N Frequency Synthesizer in 90nm CMOS

Having the radio operate at 60GHz is not free. One of the biggest challenges is to generate a stable mm-wave carrier signal to be used to tune to the right channel in reception or modulate the information up into the right channel for transmission. Mm-wave voltage-controlled oscillators (VCO) in CMOS technology have been demonstrated. However, a simple oscillator is not able to provide the stability and spectrum pureness required for the radio. These oscillators need to be controlled by a feedback loop (i.e. Phase-Locked Loop, PLL) that uses a high-purity crystal oscillator as a reference. Unfortunately, these precise reference oscillators are typically available at lower frequencies of few tens of megahertz. Therefore, before comparing to the reference frequency, the signal at the output of the oscillator has to be divided down to the same frequency of the crystal oscillator. Realizing a mm-wave frequency divider that can perform this function is very challenging even in today’s sub-100nm CMOS technologies.

ILFD_for_Synth.jpg
Figure 1. The concept of an injection-locked frequency divider (ILFD). The ILFD is essentially an oscillator with a free running frequency ffree (top figure). If a signal around ffree or its harmonics is injected onto the divider as shown in the bottom figure, the divider tries to synchronize to the injected signal, i.e. “locks” to it, and the output tracks the injected signal rather than oscillate at its free-running frequency.

At ISSCC 2008 my colleagues at Intel, Texas Instruments and Georgia Institute of Technology, Rajarshi Mukhopadhyay, Ashoke Ravi, Joy Laskar, Yorgos Palaskas and I announced a 39.1-to-41.6GHz ?? Fractional-N Frequency Synthesizer in 90nm CMOS. The proposed mm-wave PLL uses a particular breed of frequency dividers called injection-locking frequency dividers (ILFD) to divide down the VCO signal to lower frequencies where conventional dividers can then be used. An ILFD can operate at very high speed with a reasonable amount of power, but over a limited range of frequencies. To overcome this limitation, a digital-calibration technique has been implemented. How do these dividers work? An injection-locking divider is very similar to an oscillator. When it is not disturbed by any external signal, it oscillates at its own free-running frequency. Due to non-linear effects, some nodes in the circuit experience signals at integer multiples (harmonics) of the output free-running frequency. If an external signal at a frequency close to one of those harmonics is injected in the node, the whole divider will try to synchronize to it, aka “locks” to the injected signal. For example, assume that the free-running frequency of the divider in figure 1(a) is ffree and one of its internal nodes has some 4th harmonic content, i.e. 4ffree. If now an external signal at a frequency finj ~ 4ffree is injected on that node, the divider will lock to it and therefore the output signal of the locked divider becomes finj/4. This implements a division by 4. However, if the injected frequency is too far from the harmonic of ffree, the divider cannot lock anymore.

calibrated_for_synth.jpg
Figure 2: The technique used to calibrate the injection locked divider. With a fixed VCO frequency fVCO, the output of the divider should be constant (fVCO/4) if the divider is locked. This observation can be used to see if the divider is “tuned” right.

We can extend the frequency range over which the divider locks by making sure that its free-running frequency is always close to one fourth of the injected frequency. Assume that we can control the free-running frequency of the divider by an external voltage Vilfd and that we want to use the divider to divide the VCO frequency by 4 (Figure 2). The free-running frequency of the divider can be calibrated so that it is close to fVCO/4. However, since the PLL is not locked yet (we still need to calibrate the divider that is used by the PLL to achieve lock), the VCO frequency is not known. How can we calibrate the divider? The idea is shown in figure 2. The signal from the VCO is injected in the divider. The frequency is unknown, but it is kept fixed. Then the voltage that controls the ILFD free-running frequency is swept while the frequency of the signal at the output of the ILFD is monitored (filfd). When the divider is not locked, its output frequency is equal to the free-running frequency and so it will change by changing Vilfd. However, when the divider locks onto the VCO signal, filfd becomes one fourth of the VCO frequency and stays constant over the locking range, no matter what the Vilfd control is. After that, the divider unlocks again, and its output frequency again tracks Vilfd. By simply looking at the plateau in the plot in figure 2, we can recognize the range of Vilfd over which the divider is locked (shaded area in figure 2). To center this range around the VCO input frequency we just have to select the center of such range as the calibrated Vilfd.

The proposed PLL is the first ever fractional-N CMOS mm-wave synthesizer and uses an injection-locking divider-by-4 after the VCO. One division by 4 instead of two successive division by 2 can cut the power consumption by half. However, the locking range of a divider-by-4 is typically smaller compared to a divider-by-2. The calibration technique explained above enables the use of such low-power divider over the required frequency range. The fractional-N synthesizer is able to generate frequencies with a very fine resolution, few kilohertz in our case. This capability can be used to adjust for variation of the reference oscillator, so that a cheaper crystal, with less accuracy in the absolute oscillation frequency, can be used. This further reduces the overall cost of the radio.

Stefano Pellerano was born in Bari, Italy. He received the Laurea Degree and the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2000 and in 2004, respectively. During his Ph.D., his activity was focused on the design of fully integrated frequency synthesizers for wireless LAN applications. In 2003 he has been a consultant with Agere Systems (former Bell Labs) in Allentown, PA. He is now with the Communications Technology Lab of Intel, Hillsboro, OR. His recent research interests include fully-integrated MIMO transceivers, mmWave radios and digital-style phase-locked loops for WiFi/WiMax applications in CMOS technology.

3 Responses to Stefano Pellerano on 60 GHz Radios

  1. Noureddine Outaleb says:

    Hello,
    I am interested to see some 60 GHz Intel CMOS transceiver performance if any?
    Thanks,
    Noureddine Outaleb,
    Senior RF Designer
    Nortel

  2. Ran SHU says:

    I am so glad to read this kind of technology literature. Hopely have chance to exchange ideas with you.
    Ran SHU, Technology Institute of Berlin