One of the consequences of widespread use of wireless is that the spectrum is getting crowded. Radio standards must be designed to operate under this rather hostile environment with the presence of a lot of blocking signals in the channels adjacent to the one your radio is working in. It turns out that the standards account for the worst possible scenario, and all radios are designed to meet that specification all the time whether blockers are present or not. This means that a receiver design consumes power whether a blocker is present or not. This is rather wasteful and an obvious way to fix it would be to have a way to reduce power of the receiver if we can determine that there are no blockers present.
|A typical radio is designed to handle the worst case blocker. The dynamic range requirement (hence power) can be dramatically reduced if that blocker were not present.
Another challenge a radio designer faces is that with transistor scaling the analog voltage reduces and analog design gets more challenging. This is compounded by the fact radios have to support multiple standards with different bandwidths and data rates. The trend in the industry is to make the radio more digital by pushing most of the analog filtering to the digital domain. This means that we need to have an Analog-to-Digital Converter (ADC) that has a very high dynamic range that is a significant design challenge and takes more power.
At ISSCC 2008, colleagues at Intel, Cornell University and Georgia Institute of Technology Pukar Mala, Kevin Kornegay, K. Soumyanath and I presented an ADC that allows us to tackle both these challenges simultaneously. The sigma-delta ADC is designed for a radio that has minimal filtering in the analog domain, just a programmable one pole and a fixed anti-alias filter. A sigma delta ADC exploits the speed of the modern CMOS process to improve the resolution.
The block diagram of the baseband section of the receiver is shown below:
|The block diagram of the ADC in a WiFi/WiMAX receiver. The Simple spectrum analyzer (SSA) uses the low resolution high frequency measurement in the ADC to determine the dynamic range required in the ADC according to the interference scenario.
The core of the sigma-delta has been designed to attain a 12 bit dynamic range in the worst case situation. However it takes most power in this mode. If we can figure out that there is no significant blocker present we can dial down the power of the ADC and possibly other components of the radio. This would allow us to operate in the most optimal power mode while allowing us to survive large blockers.
Sensing the interference environment of the ADC can be performed for free using existing hardware. A sigma-delta ADC can convert the input signal over a large bandwidth with very low resolution. However if we just care about the power of the channels near the signal, the low resolution is sufficient to allow power measurement. We use the unshaped high speed output of the ADC to determine if/where the blockers are present and their power. With this information about the surrounding spectrum we can determine how much dynamic range is required in the ADC and appropriately adjust the power dissipation.
The proposed ADC is the most power efficient ever published for this type of ADC. It takes only 0.27pJ/bit of data converted. The power of the ADC can be reduced from 28mW all the way down to 12mW if reduced dynamic range is allowed when minimal blockers are present. This power reduction is achieved by shutting down portions of the ADC. This small power dissipation is achieved by using scaling friendly architecture that pushes the operation speed of the ADC as high as possible. The ADC uses digital arithmetic to replace the traditional analog summing allowing lower power and scalability.
Another feature of the sigma-delta ADC is the ability to trade off dynamic range for conversion bandwidth. The dynamic range is increased if the conversion bandwidth is reduced. This feature is exploited for WiMAX channels that are 2.5MHz to 20MHz wide to reduce power consumption in these modes. The reduced power consumption is achieved by shutting portions of the ADC rather than reducing the sampling frequency. The sampling frequency of the converter is kept constant for all bandwidths of operation. This ensures that the anti-aliasing requirement of the ADC does not change. Very minimal change in the analog filtering is required in the WiFi/WiMAX modes as the channel select filtering is primarily done in the digital domain.
The ability of the ADC to measure large bandwidths allows us to be aware of the surrounding spectrum of the radio. This information can be used in many ways. We could select the optimal channel to communicate based on this information. This would enable the lowest power operation of the radio to extend battery life. Future standards will fully exploit this technology. This work provides the first circuit implementation of this scheme.
received his PhD degree in Electrical and Computer Engineering from the Carnegie Mellon University, Pittsburgh PA in 2002. From 2002 to 2004, he was Product Architect at IC Mechanics Inc, Pittsburgh PA. He has been a Research Scientist at Intel Corporation, Hillsboro, OR since 2004. His research interests include RF and mixed signal circuits for WLAN transceivers.