Yorgos Palaskas on a 65nm CMOS Power Amplifier for multi radio

Power amplifiers are used in wireless systems to transmit the desired information from the user device to the base station. Power amplifiers used in cellular systems typically deliver significant amounts of power (~1Watt) in order to be able to communicate over large distances (few miles). The modulation used in such systems is usually optimized to reduce the power dissipation of the power amplifier. For example, in GSM the information of the signal is encoded in the phase of a sinusoid waveform only (rather than phase and amplitude), which allows the use of very efficient switching PAs. (Switching PAs operate on 0-1 signals. Because the transistor operates as a switch, switching PAs usually have substantial efficiency advantages over more conventional PAs, especially in CMOS processes that are optimized for optimal switching operation for the digital circuits). Modulated waveforms optimized for PA power dissipation give good PA efficiency but at the same time result in suboptimal utilization of the available bandwidth and reduced data rates.

65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation


Contrary to cellular systems, Local Area Networks (e.g. the Wi-Fi systems used in most laptops today), cover small areas but require much higher data rates. The small area of coverage relaxes the output power requirements of the PA, but the higher data rates result in more complicated modulated waveforms with wider bandwidths and with both amplitude and phase information for better bandwidth utilization.

Upcoming wireless standards like WiMAX and 3G-LTE (Long Term Evolution) aim to deliver WiFi-like data rates over cellular-like distances. This results in challenging transmitter and PA designs due to the high power (~1 Watt) and complicated modulated waveforms.

The ~1Watt of output power is a big challenge in itself. 1 Watt corresponds to 10V across a 50 Ohm load, making PAs sensitive to breakdown of the transistors due to excess stress across the device (for example in a CMOS device the gate oxide will “break” if a large voltage is applied across it). Circuit techniques like impedance transformation using matching networks and cascading are used to alleviate the stress on the active devices. In the past, researchers have been able to demonstrate PAs with ~1Watt power using more exotic/expensive technologies or older CMOS processes (e.g. 90 or 180nm CMOS). Older CMOS processes have thicker oxides and are less susceptible to breakdown.

At ISSCC 2008, my colleagues from Intel and University of Washington, Jeff Walling, Hasnain Lakdawala, Ashoke Ravi, Ofir Degani, K. Soumyanath, David Allstot and I announced a PA that has been implemented in a scaled digital 65nm CMOS process. This complicates the PA design due to the thinner oxide. At the same time, however, it allows integration of the PA with the rest of the transceiver which has to be implemented in a modern CMOS process because of the intensive digital processing required in wireless communications. Integration of the PA with the rest of the transceiver will result in reduced cost by eliminating external amplifiers typically implemented on special expensive analog/RF processes (e.g. pHEMT).

A switching amplifier (class-E) was used in our system for improved efficiency and longer battery life. Switching amplifiers achieve good efficiency but they cannot pass amplitude information, only phase (recall that modern standards require both amplitude and phase information to maximize bandwidth utilization). Amplitude variation in switching power amplifiers is sometimes introduced using complicated/expensive schemes like supply modulators that change the supply of the switching PA to adjust the output amplitude. Our paper proposes an alternative technique where the Pulse Width (duty cycle) of the input signal driving the switching PA is adjusted to give different amplitudes.

Pulse Width Modulation
Changing the Pulse Width of a 0-1 signal changes the amplitude of the fundamental frequency. Such a Pulse-Width-Modulated 0-1 signal can be used to drive a switching PA, resulting in good efficiency (due to the switching PA) while maintaining the amplitude information.

To understand the technique, consider two pulse-trains with different duty cycles as shown in the figure. The pulse train with the smaller Pulse Width has a smaller fundamental component (which is what matters after filtering). By adjusting the Pulse Width of the signal driving a switching PA we can introduce amplitude information while still maintaining the switching nature of the PA (the PA is still driven by 0-1 signals). The proposed technique moves some of the burden of introducing amplitude information to the digital domain (i.e. generate pulses with appropriate Pulse Width) where it might be easier and more economical to solve rather than conventional approaches (e.g. supply modulation), especially for a fast modern process like 65nm CMOS. The technique, in the form presented in the paper, can be used to introduce limited amplitude variation (about a factor of 2) which is enough for some wireless standards. Many standards also require the average output power to be controlled accurately in order to minimize interference between different devices and to reduce power dissipation (when the device is close to the base station we do not need to transmit full power). The proposed scheme can also be used there to vary the average output power for such systems.

Our PA has been fabricated in a low-cost 65nm CMOS process with no expensive analog features and delivers a peak power of 28.6dBm which is close to 1 Watt (30dBm). Our work has demonstrated that varying the Pulse Width of the driving signal is a viable technique for introducing limited amplitude variation required for better bandwidth utilization. Our work is continuing to meet the very aggressive requirements of a WiMAX compliant transmitter. Stay tuned.

Yorgos Palaskas received the Ph.D. degree in Electrical Engineering from Columbia University, New York, in 2002. Since then he has been with the Communications Technology Lab of Intel Corporation, in Hillsboro, Oregon. He is currently a Lead Design Engineer doing research on wireless transceivers for WiMAX-WLAN and 60GHz in nanometer CMOS technologies.

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