Krishnamurthy Soumyanath on ISSCC: Research steps to a Digital Multi Radio

Wireless communication is growing so fast that soon it might be difficult to get a decent wireless connection at your favorite coffee shop. At the Communications Circuits Lab of Intel Corporation, we have been doing research on techniques that will allow better wireless connectivity in today’s crowded spectrum environment. Three such works are being presented at the International Solid State Circuits Conference (ISSCC) in San Francisco which begins February 3. In conducting this research, we worked closely with researchers at Georgia Tech, Cornell University and the University of Washington which continues a long trend Intel has of collaborating with academia.

Now, time for the qualifier that our legal department makes me add: All of these papers below represent research. These technologies are not yet in Intel radios and I am making no claims at this time as to when or if they will ever be in an Intel radio. OK, done with that part. Let’s take a look at the papers. The papers are being presented on Wednesday, 6 Feb so I cannot divulge too much about them here. On 6 Feb, my colleagues will post individual blogs about each of these papers so be sure to check back on Wednesday.

From Research to Product Prototype

There is one radio paper from Intel at ISSCC that is from one of our product groups. This paper, “90nm 802.11agn WLAN 1×2 MIMO Multi-Band CMOS transceiver with an integrated FE” is announcing a product prototype that is the result of research we presented two years ago at ISSCC. This solution is a power efficient dual band transceiver with full power on the chip and an integrated dual band LNA. It offers advanced digital pre-distortion calibration provides excellent performance and system stability. Combined, these enable high performance and low power consumption in a small form factor. I am looking forward to seeing this radio available one day.

90nm 802.11agn WLAN Multi-Band CMOS transceiver

WiFi/WiMAX in one

The paper “A 28mW spectrum-sensing reconfigurable 20MHz 72/70dB SNR/SNDR DT ?? ADC for 802.11n/WiMax receivers” presents the lowest power 802.11n ADC and the first reconfigurable ADC for 802.11n and multi radio applications. This ADC senses the spectrum around the received channel and adjusts the system for best performance depending on the interference environment. The ADC delivers 0.27picoJoule/conversion figure-of-merit at the highest signal-noise ratio. This mode is a 3X improvement at 2X the bandwidth of previous work leading to high performance and low cost.

Spectrum-sensing reconfigurable ADC for 802.11n/WiMax receivers

Near 1 Watt of Power for Long Reach

The paper “A 28.6dBm, 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation” reports on the first integrated power amplifier in 65nm CMOS and has a 28.6dBm (hence, wide coverage) power output. This power amplifier uses Pulse-Width modulation to introduce amplitude information required for best utilization of the limited available bandwidth. It is implemented in a 65nm CMOS process, with a die area of 1.3×1.6mm2, for easy integration. The PWPM technique enables higher bit rates by allowing us to use amplitude information in addition to the phase information. Demonstration at a high data rate will be undertaken as a future research investigation.

65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation

60 GHz

The paper, “A 39.1-to-41.6GHz ?? Fractional-N Frequency Synthesizer in 90nm CMOS” presents the first ever mm-wave 60GHZ CMOS synthesizer with <3kHz frequency resolution. The CMOS frac-N synthesizer that can be used for very accurate frequency generation in a millimeter wave transceiver. This synthesizer is a fundamental building block for low cost integrated mm-wave radios. A 60GHz radio could offer a 5 Gb/s data rate which would enable a full HD movie to be downloaded in less than 1 minute compared to 1.5 hours for today’s WLAN.

Fractional-N Frequency Synthesizer in 90nm CMOS

All of these designs have been implemented in heavily scaled CMOS processes (65nm and 90nm) and manage to exploit the phenomenal transistor speed achieved after many decades of Moore’s law to improve the radio performance. These research advances are each individual steps along the way to a nearly fully digital multi radio that will be required in the near future to enable small form factor devices like MIDs to be able to connect anytime, anywhere.

Krishnamurthy Soumyanath is an Intel Fellow and director of the Communications Circuits Research Lab where he is responsible for leading research and development activity on circuits and architectures for next-generation transceiver devices.

Comments are closed.