Enforcing Moore’s Law Through Technology Research (guest blog)

As an editor of the Research@Intel blog, I sometimes have the opportunity to share a guest post to complement those coming from our regular bloggers. Today’s post comes from Mike Mayberry of Intel’s Technology & Manufacturing Group. Mike is Director of Components Research, the group at Intel which does process technology research.

In this blog, I’ll relate some of the recent advances in compound semiconductors, but first a little background. There’s an old joke that “Gallium Arsenide is the technology of the future, never the technology of the present” and like all jokes there’s a kernel of truth. Unlike silicon, a compound semiconductor is made up of two elements, gallium and arsenic for example (GaAs). Using two elements means more opportunity to tune the materials for performance or optical properties but also makes the challenge of fabricating wafers and processing much more complicated. While 300mm diameter silicon wafers are produced in huge quantities, GaAs wafers are typically 150mm, which translates into a huge cost disadvantage. Consequently today, compound semiconductors are used in smaller scale applications where their special properties outweigh the added costs.

Despite the history, Intel has several active programs looking at compound semiconductors as a possible option for the middle of the next decade. We’re interested in compound semiconductors because of their high charge mobility. Mobility is a measure of how easily you can move charges within the material with application of an electric field. Higher mobility can produce faster devices and/or devices that require much less power. GaAs has about 8x higher mobility compared to silicon, and indium antimonide (InSb) has 50x higher. We’ve previously shown that you could achieve more than 10x improvement in power for an InSb device operating at 0.5V compared to the equivalent silicon device (see our IEDM 2005 presentation). The sticky point is that we have to figure out how to make these in high volumes, which would be impossible if we were limited to small GaAs wafers as starting material.

Most research isn’t based on sudden breakthroughs in thinking but a lot of hard work that builds on other good research. Along the way some things turn out to be easier and others harder, so having a guiding vision can separate great results from the ordinary. For this case we broke down the overall problem — how to make these in high volume — into five individual challenges:

  • Build compound semiconductor devices on silicon substrates. This would allow us to reuse the highly refined silicon infrastructure including 300mm wafers and gives us the option down the road of integrating a few specialized devices with a sea of silicon devices.
  • Find a suitable high-K gate dielectric. Due to the different surface, the silicon high-K solution won’t work as is but we can leverage knowledge we gained to help guide us.
  • Build a high performance PMOS device to go with the existing NMOS. This is needed to have power efficient CMOS logic though some special circuits can get by with just one type.
  • Build enhancement devices. Most existing work is based on depletion mode where you apply a voltage to shut them off. Power efficiency demands that those devices be normally off.
  • Make them small enough to compete with silicon transistor densities. If we stop at integrating only a few specialized devices then this is not needed but then we also won’t reap the full benefit of the technology.

We are working both in our internal labs as well as with such external groups as universities to make progress on this list of challenges.

Starting with item one, the reason people don’t regularly grow compound semiconductors on silicon is due to the mismatch in lattice spacing. That mismatch produces defects that degrade the performance of the devices. Here’s a TEM of GaAs grown on silicon that illustrates the problem. The dark wavy lines are dislocation defects that short-out the device when you try to operate it.

Picture1.jpg

To successfully grow working devices we first grow a buffer layer to absorb most of the mismatch and then we engineer a succession of thinner layers that get closer to the desired lattice spacing. It is a delicate task as the final device is a few 10s of nanometers thick and so currently we use molecular beam epitaxy (MBE) to deposit each atomic layer individually. Here’s a TEM of the quantum well (the region where electrical switching occurs) and you can just make out the individual atomic layers.

Picture2.jpg

As of this summer we have achieved success at fabricating high performance devices using two material types, InSb and InGaAs, and in each case they perform as well as their counterparts on GaAs wafers. Here is the maximum frequency of depletion mode devices plotted against power dissipation. You can see the two InGaAs curves overlap each other and also are significantly better, both higher performing and less power, than equivalently sized silicon devices.

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This is a major milestone! In the past others have made poorly performing devices on silicon but these are the first reports of high performance devices on silicon. We have published these results recently including the graph above (IEEE Electron Device Letters, Vol. 28, No. 8, August 2007, pp.685-687). At the upcoming IEDM conference in Dec. we will show even newer results for much thinner buffer layers as well as data on enhancement mode devices (#4 on the list).

As usual, we pause briefly to celebrate and then we go back to work on the rest of the list. We’ve made considerable progress in generalizing the growth solutions as we’ve demonstrated by the multiple material types and this will give us flexibility and choices for further research and development. We know Moore’s Law can continue if we invent the right things and it is our job to make sure Intel can continue to deliver advanced technology on time, every time.

Editors Note: Please address comments to Mike — I’ll pass them on to him.

4 Responses to Enforcing Moore’s Law Through Technology Research (guest blog)

  1. Building high quality devices in III-V materials on a silicon substrate is a significant achievement. However, the freedom to tune bandgap and lattice parameters that compound semiconductor bring has a price that is often unacknowledged. Economic production of devices demands alomost perfect homogeneity in the x-y direction and perfect INhomogeneity in z. Abrupt layer interfaces, with close-to-invariant materials properties from edge to centre.
    My experience suggests there is a disconnect between the conventional silicon world and the conventional III-V world, driven by the fact that silicon is such a wonderful material. Enormous effort was required to get such things as pHEMTS on GaAs or PiN structures on InP to a decent yield level, spanning both the nature of the substrate/epilayer interaction and the complexities of epitaxy at 500, 75, 100 and 150mm. The challenges in going further on any substrate must be immense. Of course the funds required to do such work pale in comparison to the cost of a 300mm fab. But nevertheless, the change required in the way we approach the problems of crystal growth, the materials science toolkit is vast.
    Just my two cents worth – with the benefit of 20 years working on InP and GaAs homogeneity problems

  2. Jeff LaCoss says:

    This is exciting work! Keeping up with throughput/density is a major challenge for the entire semi industry, and it encouraging when Intel and others write about their developments.
    While OPS/desktop is clearly the major economic driver, I am most curious about the possibility of operating III-V devices at elevated temperatures – say 250C. This would open up an entirely new area of instrumentation in hazardous process monitoring and control. Being able to build devices that can run where silicon won’t and where solder melts would be a major step forward.

  3. Fabio Fumi says:

    Results obtained on single devices are certainly exciting, but I remember from my experience on GaAs MMICs that one key feature of that technology is not only the device characteristics, but also substrate isolation. This allows to build passive elements suitable for microwave frequencies with relatively little hurdle.
    How would this be addressed on Si substrates, which are inherently conductive?
    In any case, integration is always the main roadmap to pursue. Congratulation for the results obtained!

  4. Mike Mayberry says:

    Thank you for your comments. These are indeed hard problems to solve on a large scale and we are realistic that we have a lot more work ahead of us. For this particular work, we are in effect trading one hard problem, making nearly perfect large III-V wafers, for a different problem, growing quality III-V layers on a silicon substrate. By this path we take the large scale III-V crystal growth out of the problem and substitute the problem of depositing uniform atomic layer films. The latter can leverage infrastructure developed for silicon manufacturing. By going this route we also open up new avenues for eventual mix and match of different devices on the same silicon substrate.