Steve Pawlowski is Inventing the New Reality

posted by Dane Unruh (Owen Media) on August 22, 2008

Tick Tock. I found an opportunity to chat with Steve Pawlowski - one of the minds behind Intel’s latest Tock - as I was checking my own digital pulse in the IDF Upload Lounge on day 2 of the Intel Developer Forum. While the lounge had a very Space Odyssey 2001 retro-futuristic fantastic vibe, Steve was all about Nehalem and beyond. Maybe there is some irony there.

For those of you who are not familiar with Steve, he is a man of many complementary hats at Intel - an Intel Senior Fellow, CTO of the Digital Enterprise Group, and GM of Architecture and Planning. Both techie and accessible, Steve is uniquely suited to provide a coherent account of this next generation of Intel’s microarchitecture as well as convey what lies beyond.

To be sure, Nehalem microarchitecture is a whole new thing. While taking advantage of the darling of last Fall’s IDF, hafnium-based Intel 45nm Hi-k metal gate silicon technology, Nehalem adds capabilities that are above and beyond Intel Core microarchitecture. Some of the highlights here include an integrated memory controller, multi-level shared cache, and a complete redesign of the system interconnect. In Steve’s words, the front side bus had run its course. Well spoken. The front side bus has been scaling rather well for quite a long time, but when instructions per clock increase on average 20% - 25% per microarchitecture refresh, it was only a matter of time before these high performance, many-core processors demanded a new system interconnect. What is replacing the front side bus? Point-to-point high-speed QuickPath interconnect.

Of particular interest here at IDF have been Nehalem’s new power management capabilities. Nehalem takes a different approach than the traditional technique of shutting down inactive cores by cutting their active power - a method that doesn’t prevent voltage leakage. Nehalem’s new power gating technology addresses the leakage current and brings an inactive core’s power dissipation to next to nothing. The power saved can then be diverted to cores that are being used by actually increasing their clock speed. Power stingy indeed.

Beyond Nehalem, the future looks fast. Steve assured me that he and Intel have not run out of ideas for even the traditional ways of increasing instructions per clock. There will be new technologies and new capabilities. Intel’s 32nm silicon technology is on the horizon, and Steve is confident that Intel engineers can continue to shrink the transistor well into the next decade. This being said, Steve is looking to new computational models to find ways to increase performance and efficiency. Of particular interest to Steve are biological models of computing - generating complexity from very simple rules. These models tend to use a very significant number of devices that individually aren’t necessarily the fastest or smartest, but when combined they generate considerable performance. Think autopoiesis. Think ant colony.

Top of mind for Steve these days - aside from tying flies and how the Portland Trail Blazers will perform this next season - is how to continue to provide the level of innovation that the technology industry is accustomed to, and do it in an economical fashion considering the trend in economies of scale. Or, rather, Intel has got to keep up with Intel. It is a challenge that Steve is less worried about than he is excited. I imagine that what Steve’s exploratory research team is developing in silicon photonics will help to ease his mind. Tick Tock.

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tagged: IDF2008, intel, intel developer forum, nehalem, steve pawlowski