A Time of New Beginnings: QuickPath, Power Control, Larrabee and SSDs

posted by Glenn Hinton on August 21, 2008

In the computer world there are times when new technologies enter the scene that set a new direction and change how the next decade evolves. For example, in 1995 the Pentium Pro (original P6 micro-architecture) with its new high-performance out-of-order execution micro-architecture and its glueless multi-processor FSB support brought a new level of performance and capability to the volume microprocessor arena. Our new high performance Nehalem micro-architecture still leverages significantly from the original P6 micro-architecture 13 years later and our current Core 2 FSB system interconnect evolved from the original P6 FSB.

There are 4 such revolutionary technologies being discussed at IDF this year: 1) Nehalem’s new Quickpath system topology with a very high performance integrated memory controller and its QPI system interconnect link, 2) Nehalem’s advanced power management with its Power Control Unit and Power Gates to give dynamic power control for higher performance Turbo Mode and very low power sleep states, 3) Larrabee as an architecture which gives very high performance and flexible x86 computing for high end graphics and data parallel application performance, and 4) the arrival of high speed flash memory to break the IO bottleneck, starting with Intel’s new Ephraim SSD. Each of these capabilities will have a significant impact on Intel’s computing futures for the next decade.

Intel microprocessors have used an evolved form of the P6 front-side bus for the last 13 years which enabled glueless multi-processor systems and efficient single processor systems. It has evolved significantly from the original 66MHz version in 1995 to the 1333 MHz quad-pumped FSB versions of 2008. QPI marks a new era of scalable system interconnects for Intel systems. Together with the very high performance three channel integrated memory controller it enables very scalable and high performance multi-processor systems. These provide a tremendous performance gain for our new Nehalem systems and set the direction for our scalable platforms for many years to come.

Power management has advanced year over year for the last 10 years or so starting with our mobile optimized CPUs and chipsets. They each improved upon the hardwired power management logic of the previous generation. Nehalem’s new Power Control Unit (PCU) breaks from the past and uses an on-chip micro-controller with dynamic power sensors to actively manage the entire multi-core chip power and performance. In conjunction with this Nehalem has new Power Gates that enable idle cores to be completely shut off from the power supply reducing the leakage to near zero for sleeping cores. These Power Gates remove the multi-core penalty of leakage when running single or few threaded workloads. The PCU can dynamically alter the voltage and frequency of the CPU cores to give a big performance boost when most cores are idle or running lower power workloads with its new Turbo Mode capability. This active power management by an on-chip micro-controller gives big benefits and sets the path for our power management going forward.

Larrabee is a radical change in how graphics is done in the platform. It uses many x86 cores with a new 16-wide vector unit per core with some special graphics HW assists to provide very high performance and capable graphics. It has the CPU programmability and the GPU parallelism. It allows for a very efficient and scalable SW renderer for graphics and is flexible to also provide tremendous performance for many data parallel applications in other areas. This marks a significant change in how graphics and high data parallel throughput computing will be done in the future.

In the last 10-12 years our CPUs have sped up 50-60x for single stream performance and 175x for threaded performance (based on measured average of SPECINTrate + SPECFPRate across this time period). The disk drive has only sped up about 30% for typical random access usage in this same timeframe. We compensated by adding more and more DRAM to buffer the need to go to the disk. This DRAM buffering works pretty well for many steady-state applications but fails miserably for transients like starting up new large applications and rebooting and for workloads that really need non-volatile storage. DRAM also costs a lot more per giga-byte than NAND flash memory and has a lot higher power, hurting the battery life for laptops. High speed NAND flash, starting with Intel’s high performance SSD, speeds up typical IO access patterns by more than an order of magnitude compared to high performance desktop disk drives and even more compared to low-power laptop disk drives. This new high performance flash-based IO will enable our new high end multi-core CPUs to stand out and accelerate even IO bottlenecked workloads. The faster the CPU is the more the fast high speed flash IO gains in previously IO bound tasks that now become CPU bound. All SSDs out there are not equal in terms of performance, reliability, or power management. Intel’s new SSD provides stunning new responsiveness in IO dominated tasks and does it with great power management and reliability and does this with weight and size reduction vs disk drives. Intel’s performance SSDs usher in this new NAND flash accelerated IO era for our high end computing platforms.

Each of these 4 new paradigm shifting capabilities will provide tremendous new benefits to computing systems and will affect our future platforms for many years to come.

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tagged: glenn hinton, GPU, intel, larrabee, NAND Flash, Nehalem, parallelism, PCU, power, quickpath, solid state drive, SSD