Category Archives: Performance and Optimization

Ultrabooks are here and so is our new community!

Without a doubt, one of the most exciting developments in the tech world for 2011 was the introduction of the Ultrabook.  We put a reference design out there and OEMs took it and ran with it.  Most of the models that arrived were slim, sleek, powerful and yet power-efficient.  I brought one of the current [...] Read more >

Register for Intel(R) Technical Presentation "Analysis of hybrid applications with the Intel(R) Cluster Studio XE 2012"


Gergana Slavova, Technical Consulting Engineer, will be presenting “Analysis of hybrid applications with the Intel(R) Cluster Studio XE 2012″ on Dec 7th at 9am PDT. Please register! Read more >

Paving the Road to OpenMP 4

The dust of SC’11 starts to settle and several announcements around OpenMP have been made in Seattle. There has been a change in the OpenMP Architecture Review Board and Language Committee. Several new members have joined the committee and started to actively participate in the development of future OpenMP versions. Also, Michael Wong (IBM) has [...] Read more >

MIC architecture support by software tools – SC11 wrap-up

This week we demonstrated the Knights Corner co-processor at SC11 and we had many developers demonstrating real results with the prototype systems. During the “SC11 season,” a number of tool vendors announced they will be providing versions of their software tailored to supporting MIC architecture, starting with the Knights Corner co-processor. Here are the ones I know [...] Read more >

quick chat about MIC architecture with Mike Dewar, NAG

I ran into Mike Dewar at SC11 today as the exhibition draws to a close.  Mike is the CTO of NAG Ltd. – a company we’ve had the good fortune to work with for years. NAG is one of a handful of companies that have been providing feedback on our Knights Ferry (prototype MIC architecture). [...] Read more >

Seeing One TeraFlop, the software side, and feeling a bit emotional

I’ve known this day was coming – but when I saw Knights Corner clearly sustaining a TeraFlop (DGEMM, wide range of block sizes) – I was surprised by my emotional reaction inside. Hard to describe; it was a good feeling. Tuesday November 15, 2011, we showed a Knights Corner co-processor for the first time outside [...] Read more >

Open Parallel: Optimizing Web Performance with TBB

Open Parallel is a research and development company that focuses on parallel programming and multicore development. We are a bunch of highly skilled geeks from various backgrounds that work together on problems in parallel programming and software development for multicore and manycore platforms. At LinuxConf (LCA2010) James Reinders gave a talk about the Threading Building [...] Read more >

AES Counter Mode details (Intel AES-NI implementation)

In this article we’ll take a closer look at AES counter (CTR) mode implementation from Intel® AES-NI library (it can be downloaded from http://software.intel.com/en-us/articles/download-the-intel-aesni-sample-library/). AES stands for Advanced Encryption Standard and it is a symmetric encryption standard. More detailed information about AES at http://de.wikipedia.org/wiki/Advanced_Encryption_Standard. AES-NI refers to Intel® Advanced Encryption Standard (AES) Instructions Set which [...] Read more >