Category Archives: Parallel Programming

Intel Aids Search for Lost DaVinci Masterpiece

In the Palazzo Vecchio in Florence, Italy, a feverish search occurs seemingly in slow motion. In order to make progress in the search, a team of researchers from the University of California/San Diego has been inventing a brand new field of work called art forensics. Armed with innovative new portable sensing devices and Intel technology, […] Read more >

Looking Ahead to 2012

Well, I reflected on 2011 in my last blog, so now it’s time to look ahead. My basic role will remain unchanged – I help users of our Intel® Software Development Products to achieve better performance on their applications. I will still be updating our training materials and videos for the latest mainstream Intel processors. […] Read more >

Scalable Memory Pools: community preview feature

In TBB 4.0, we introduced new community preview feature (CPF) – the scalable memory pools. See the TBB Reference Manual (D.4) for formal and detailed description. In this blog, we will present them less formally and discuss what changes can be made. Motivation We had vague requests from customers to implement a memory pool (Wikipedia […] Read more >

My 5 Favorite New Intel® Software Development Product Features of 2011

It’s been a big year for us in the Intel Developer Products Division. We released Intel® Cluster Studio XE and Intel® Parallel Studio XE Service Pack 1. We continued to plan and design our products to provide support for the compute continuum. And of course we worked to grow our community of developers. Throughout the […] Read more >

The Last Show – Parallel Programming Talk #130 – Parallel Manifold with Jim Dempsey

It was sad when “Friends” ended, and who can forget the endings of “MASH” and “Jerry Seinfeld”? So it goes with ISN’s “Parallel Programming Talk” show.  Our last show was a fitting end to 130 radio and Web TV programs about all things Parallel. It wasn’t a “montage” or “retrospective” show but simply a great […] Read more >

MIC: Stepping-stone to Quantum Computing?

I was reading Quantum Computing for Computer Scientists by Noson S. Yanofsky and Mirco A. Mannucci while I was on the treadmill last night. I started out reading the description of Shor’s algorithm (for factoring integers) and thought that implementing this on a classical computer (in parallel, of course) would make an interesting problem for the Intel […] Read more >

Some Performance Advantages of Using a Task-Based Parallelism Model

As part of my focus on software performance, I also support and consult on implementing scalable parallelism in applications. There are many reasons to implement parallelism as well as many methods for doing it – but this blog is not about either of those things. This blog is about the performance advantages of one particular […] Read more >

Register for Intel(R) Technical Presentation "Analysis of hybrid applications with the Intel(R) Cluster Studio XE 2012"

Gergana Slavova, Technical Consulting Engineer, will be presenting “Analysis of hybrid applications with the Intel(R) Cluster Studio XE 2012” on Dec 7th at 9am PDT. Please register! Read more >

Pipeline Speak, Part 2: The Second Part of the Sandy Bridge Pipeline

Last week I posted a blog explaining the front-end of the pipeline on Intel(R) Microarchitecture Codename Sandy Bridge. Today’s blog completes the discussion of the pipeline by explaining the back-end, and then why it’s helpful to know this stuff in general. The Back-End The back-end of the pipeline is responsible for executing the micro-operations the […] Read more >

Pipeline Speak: Learning More About Intel® Microarchitecture Codename Sandy Bridge

As I’m sure you know, modern processors employ a technique called pipelining to increase instruction throughput. In a pipeline, various dedicated pieces of hardware on the processor each perform particular functions needed to process an instruction, on different instructions at the same time. For example, while one part of the pipeline is executing instruction A, […] Read more >

Paving the Road to OpenMP 4

The dust of SC’11 starts to settle and several announcements around OpenMP have been made in Seattle. There has been a change in the OpenMP Architecture Review Board and Language Committee. Several new members have joined the committee and started to actively participate in the development of future OpenMP versions. Also, Michael Wong (IBM) has […] Read more >

Intel® Concurrent Collections with Intel Scientist Kath Knobe – Parallel Programming Talk #129

Intel Labs Scientist Kath Knobe spent some time with Clay Breshears and Kathy Farrel on Parallel Programming Talk to talk about what’s new with Intel® Concurrent Collections, a programming language and software framework developed by Intel to express parallelism in applications.  Here is the video – at the bottom of this blog you will see topics discussed […] Read more >

MIC architecture support by software tools – SC11 wrap-up

This week we demonstrated the Knights Corner co-processor at SC11 and we had many developers demonstrating real results with the prototype systems. During the “SC11 season,” a number of tool vendors announced they will be providing versions of their software tailored to supporting MIC architecture, starting with the Knights Corner co-processor. Here are the ones I know […] Read more >

quick chat about MIC architecture with Mike Dewar, NAG

I ran into Mike Dewar at SC11 today as the exhibition draws to a close.  Mike is the CTO of NAG Ltd. – a company we’ve had the good fortune to work with for years. NAG is one of a handful of companies that have been providing feedback on our Knights Ferry (prototype MIC architecture). […] Read more >

Seeing One TeraFlop, the software side, and feeling a bit emotional

I’ve known this day was coming – but when I saw Knights Corner clearly sustaining a TeraFlop (DGEMM, wide range of block sizes) – I was surprised by my emotional reaction inside. Hard to describe; it was a good feeling. Tuesday November 15, 2011, we showed a Knights Corner co-processor for the first time outside […] Read more >