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Intel® Xeon Phi™ coprocessor Power Management Turbo Part 1: What is turbo? And how will it affect my horsepower?

INTRODUCTION AND PURPOSE:

This is the first of a series of blogs looking at Turbo: What it is and how it impacts software.

This series discusses basic concepts, terminology, how Turbo relates to thermal profiles, when Turbo is useful, and whether Turbo can impact application design.

This is a follow on to my previous series of blogs on power management.

  • ·         Intel® Xeon Phi™ coprocessor Power Management Pt 0: Introduction and inquiring minds
  • ·         Intel® Xeon Phi™ coprocessor Power Management Part 1: P-States, Reducing power consumption without impacting performance
  • ·         Intel® Xeon Phi™ coprocessor Power Management Part 2a: Core C-States, The Details
  • ·         Intel® Xeon Phi™ coprocessor Power Management Part 2b: Package C-States, The Details
  • ·         Intel® Xeon Phi™ coprocessor Power Management Part 3: An Intuitive Description of Power States Using Stick Figures and Light Bulbs

 

My plan is to continue this silliness with at least two more series with this power management theme:

(1)    Power management configuration: What can I do? How can I do it? And why would I want to do it?

(2)    A power management example: The gory and boring details.

I cannot guarantee that the titles will stay the same when I actually get around to writing the articles.

TURBO, TURBOCHARGERS AND HORSE POWER

Turbo really doesn’t have much to do with horsepower. You are thinking about the “turbocharger,” a device that improves the horsepower of an internal combustion engine by increasing, through overpressure, the amount of fuel/air mixture ignited per stroke. Even so, the “turbo” state of an Intel processor is at least related in concept. In modern Intel processors, “turbo” is a way of briefly accelerating software beyond the design limits of the silicon. It does this by boosting the voltage and overclocking the processor. Does this remind anyone else of a P-state? It should.

TURBO AND POWER MANAGEMENT

Any modern processor has thermal sensors. The reason is simple. If the processor gets too hot, nasty things happen. If you’re lucky, the processor shuts down. If you’re unlucky, it will continue to work – sort of – and will fail at a crucial time resulting in the inevitably loss or corruption of very important data.

The basic idea underlying Turbo is that, if the temperature of the entire processor is cool, you can boost the performance of, i.e. overclock, the processor for a limited amount of time. This is possible because the adjacent silicon and packaging material acts as a heat sink. After the surrounding material heats up and no longer acts as an effective heat sink, the processor’s power management hardware drops the voltage-frequency back to a level of performance that the silicon can maintain indefinitely.

FIRST SOME TERMINOLOGY

Before we get into further details, I need to make sure we are all using the same words in the same way. What follows is a list of processor and power management terms.

PMAX – maximum power dissipation recommended by the manufacturer (e.g. Intel)

TC (Case Temperature) – temperature measured at the geometric center of the processor package

TC-MAX – maximum Tc recommended by the manufacturer

Tjunction – temperature of a core

Tjunction-MAX – maximum allowed junction temperature before thermal throttling occurs

Hardware (HW) Threads – a HW execution context with its own registers, etc. Multiple HW threads often share the same pipeline. The OS usually sees a HW thread as a separate CPU.

Power Management (PM) Hardware – hardware circuitry that runs on the processor and implements the actual power management. Software controls some of this circuitry (e.g. P-state transitions). Much of it is invisible and not under software control (e.g. thermal throttling to avoid damage).

Power Management Software – software that runs on the processor and provides overarching control over the power management hardware. An example is the OS’s kernel power management module that controls P-state and C-state transitions.

Processor Package – the black package containing any silicon (e.g. cores), substrate, thermally conductive covering, pins, discrete components (e.g. capacitors), etc. Most people think of this black package as the “processor”.

SKU – The SKU is a product version. Though the same product (e.g. Intel® Xeon Phi™ coprocessor), different SKUs have different capabilities and price points.

Software (SW) Threads – what is traditionally thought of as an OS or application thread

TDP (Thermal Design Power) – Intel® provides this value to designers of systems using Intel® processors. It is not the maximum junction temperature or the maximum power the chip can dissipate. It is an average power dissipation for the processor when running typical consumer applications, such as word processors, spreadsheets and video playback. Its intent is as a guideline for platform designers (e.g. designers of laptops).

Thermal budget – the heat capacity available to all or part of a package before exceeding its design specifications

Thermal throttling – limiting the performance of the processor to reduce the Tjunction of its cores and so avoid permanently damaging the processor. This throttling often involves reducing the frequency and voltage of the processor (i.e. increasing the P-state).

NEXT: THE HOUSE THAT INTEL BUILT: COLD AND HOT RUNNING SILICON

REFERENCES

For those of you with a passion for power management, check out the Intel® Xeon Phi™ Coprocessor Software Developer’s Guide. It has state diagrams and other goodies. I recommend sections 2.1.13, “Power Management”, and all of section 3.1, “Power Management (PM)” for your late night reading.

Another great reference is, “Intel® Xeon Phi™ Coprocessor: Datasheet”. Its URL is http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-phi-datasheet.pdf.

You can find the previous blogs in this series at:

 

NOTE: As previously in my blogs, any illustrations can be blamed solely on me as no copyright has been infringed or artistic ability shown.

 

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Intel® Xeon Phi™ coprocessor Power Management Part 3: An Intuitive Description of Power States Using Stick Figures and Light Bulbs

AN INTUITIVE ILLUSTRATION OF A CORE AND ITS HW THREADS

This is the fourth installment of a series of blogs on Power Management for the Intel® Xeon Phi™ coprocessor.

For those of you who have read my blog presenting an intuitive introduction to the Intel® Xeon Phi™ coprocessor, The Intel Xeon Phi coprocessor: What is it and why should I care? PART 3: Splitting Hares and Tortoises too, I irreverently referred to “diligent high tech workers who labor ceaselessly for their corporate masters”. Let’s take this description a little further. In Figure A, we have one such diligent high tech worker. He is analogous to one coprocessor CPU/HW thread.

Figure A Diligent high tech worker, i.e. an Intel® Xeon Phi™ HW thread

 

There are 4 HW threads to a core. See Figure B. It’s pretty obvious so I’m not going to bother with a multipage boring description of what it means. There is also that mysterious light bulb. The light bulb represents the infrastructure that supports the core, such as timing and power circuits.

Figure B Diligent high tech workers in a room, i.e. a Intel® Xeon Phi™ coprocessor core

 

POWER MANAGEMENT: Core C0 and C1

So what does all this have to do with power management? Though it is sometimes assumed by the lower paid liberal arts students that engineers are unimaginative and boring, you and I know that, though boring we may be, we are not unimaginative. With this in mind, I ask you to visualize that on every one of those desks is a computer and a desk light.

The Core in C0: When at least one of the high tech workers is diligently working at their task. (I.e. At least one of the core’s CPUs/HW threads is executing instructions.)

CPU Executing a HALT: When one of those diligent workers finishes his task, he turns out his desk lamp, shuts down his computer, and leaves. (I.e. One of the HW threads executes a HALT instruction.)

Entering Core-C1: When all four diligent workers finish their tasks, they all execute HALT instructions. The last one finishing turns off the lights. (i.e. The core is clock gated.)

 

POWER MANAGEMENT: Core-C6

Entering Core-C6: Yes, I know it’s blatantly obvious, but I like talking to myself. As time proceeds, everyone leaves for lunch. Since no one is in the offices, we can shut things down even further in the rooms (i.e. power gating). Remember, though, that they are coming back after lunch so anything shut down must be able to be powered back up quickly.

 

Figure C A building full of diligent high tech workers, i.e. an Intel® Xeon Phi™ coprocessor

 

 

POWER MANAGEMENT: Package Auto-C3, Package Deep-C3 and Package C6

Now I’m going to stretch this analogy a little bit, but since it is fun, I’m going to keep on going.

Let’s expand this very creative analogy. Imagine if you will, a building with many rooms, 60+ in point of fact. See Figure C. Yes, I know that here in Silicon Valley, diligent high tech workers work in luxurious cubes, not stuffy offices. Unfortunately, the analogy breaks down at that point so I am sticking with communal offices.

Entering Package Auto-C3: Everyone has left the floor, so the movement sensor automatically shut off the floor lights. (I.e. the coprocessor power management software clock gates the Uncore and other support circuitry on the silicon).

Entering Package Deep-C3: It’s the weekend so facilities (i.e. the MPSS Coprocessor Driver Power Management module) shuts down the air condition and phone services. (I.e. the host reduces the coprocessor’s VccP and has it ignore interrupts.)

Entering Package C6: It’s Christmas week shutdown and forced vacation time, so facilities turns off all electricity, air condition, phones, servers, elevators, toilets, etc. (I.e. the host turns off the coprocessor’s VccP and shuts down its monitoring of PCI Express* traffic.)

POWER MANAGEMENT: Getting obsessive

Having fun with this analogy, I was thinking of extending it further into industrial campuses (a node containing multiple coprocessors), international engineering divisions (clusters with each node containing multiple coprocessors) and contracting with external partners (distributed WAN processing). Sanity and common sense prevailed and I leave the analogy as is.

NEXT: POWER STATE CONTROL AND TURBO

REFERENCES

For those of you with a passion for power management, check out the Intel® Xeon Phi™ Coprocessor Software Developer’s Guide. It has state diagrams and other goodies. I recommend sections 2.1.13, “Power Management”, and all of section 3.1, “Power Management (PM)” for your late night reading.

Another great reference is, “Intel® Xeon Phi™ Coprocessor: Datasheet”. Its URL is http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-phi-datasheet.pdf.

You can find the three previous blogs in this series at:

NOTE: As previously in my blogs, any illustrations can be blamed solely on me as no copyright has been infringed or artistic ability shown.

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