Author Archives: James Reinders (Intel)

ispc: Xeon and Xeon Phi support now

Vectorization is an industry wide challenge – and if you are interested in seeing some one of the industry leading exploration projects (and trying it on your code)… then may want to look at ispc. ispc is an R&D compiler for a C-based language that is targeted for exploring the performance available from doing SPMD [...] Read more >

Knights Corner: Open source software stack

Knights Corner: Open source software stack As mentioned in “Knights Corner micro-architecture support” the open source software stack consists of an embedded Linux, a minimally modified GCC, plus driver software. There is a package for GDB available separately as well. Links for these resources can be found at intel.com/software/mic in the article titled “RESOURCES (including downloads).” [...] Read more >

Knights Corner micro-architecture support

Knights Corner micro-architecture support How does a high performance SMP on-a-chip sound to you?  I can now share, for the first time, key details about our vision for Knights Corner (the aforementioned high performance SMP on-a-chip), and our thinking behind the software architecture and features.   There is a lot to cover here so I’ll cover it [...] Read more >

Coarse-grained locks and Transactional Synchronization explained

Coarse-grained locks, and the importance of transactions, are key concepts that motivate why Intel Transactional Synchronization Extensions (TSX) is useful.  I’ll do my best to explain them in this blog. In my blog “Transactional Synchronization in Haswell,” I describe new instructions (Intel TSX) that will improve the performance of coarse-grained locks.  Understanding coarse-grained locks and [...] Read more >

Transactional Synchronization in Haswell

We have released details of Intel® Transactional Synchronization Extensions (TSX) for the future multicore processor code-named “Haswell”. The updated specification (Intel® Architecture Instruction Set Extensions Programming Reference) can be downloaded. In this blog, I’ll introduce Intel TSX and provide a little background. Please refer to The Transactional Synchronization Extensions Chapter (Chapter 8) in the manual [...] Read more >

MIC architecture support by software tools – SC11 wrap-up

This week we demonstrated the Knights Corner co-processor at SC11 and we had many developers demonstrating real results with the prototype systems. During the “SC11 season,” a number of tool vendors announced they will be providing versions of their software tailored to supporting MIC architecture, starting with the Knights Corner co-processor. Here are the ones I know [...] Read more >

quick chat about MIC architecture with Mike Dewar, NAG

I ran into Mike Dewar at SC11 today as the exhibition draws to a close.  Mike is the CTO of NAG Ltd. – a company we’ve had the good fortune to work with for years. NAG is one of a handful of companies that have been providing feedback on our Knights Ferry (prototype MIC architecture). [...] Read more >

Seeing One TeraFlop, the software side, and feeling a bit emotional

I’ve known this day was coming – but when I saw Knights Corner clearly sustaining a TeraFlop (DGEMM, wide range of block sizes) – I was surprised by my emotional reaction inside. Hard to describe; it was a good feeling. Tuesday November 15, 2011, we showed a Knights Corner co-processor for the first time outside [...] Read more >

Let’s rename "for" to "serial_for"…

Proposal: rename for in C and C++ to serial_for No more incumbent “for.” (it was voted off the island) (let’s assume parallel_for == cilk_for in this discussion) Consider: serial_for (i=0; i < n; i++) { body } vs. parallel_for (int i=0; i < n; i++) { body } serial_for allows the values of n and i [...] Read more >

Parallelism as a First Class Citizen in C and C++, the time has come.

It is time to make Parallelism a full First Class Citizen in C and C++.  Hardware is once again ahead of software, and we need to close the gap so that application development is better able to utilize the hardware without low level programming. The time has come for high level constructs for task and [...] Read more >

Hamburg Germany – ISC’11

I’m headed to Hamburg Germany for the International Supercomputing Conference next week. We will be talking a lot about our Many-Integrated Core (MIC) Architecture and how to realize amazing performance on highly parallel applications. We have some incredible demos and partners in our booth – so I hope you can drop by to visit us. [...] Read more >